Cache Coherence for the Architect · arch

Computer Architecture · All levels

5topics
5lessons

Private caches of one address must agree on one value history. This topic builds that guarantee from the four MESI states up to fabric protocols and debug.

Four stable states and their moves.

Stable MESI edges only; transient states under races are covered in the lessons.

Lesson	What it covers
MESI states and the single-writer invariant	The four states, legal and forbidden edges, and why Exclusive exists.
Misses, upgrades, and evictions	BusRd, BusRdX, BusUpgr, acknowledgement counting, and a runnable model.
Variants and scaling	MOESI and MESIF, plus snoop broadcast against directory tracking.
ACE and CHI	An honest mapping-level introduction: CHI is not a newer ACE.
Sharing costs and coherence triage	Ping-pong, false sharing, timelines, triggers, and closure.

Check yourself Core 0 holds a line in M while core 1 holds the same line in S. Which invariant is broken, and what should the protocol have done?

Single-writer/multiple-reader is broken: M requires every other copy to be I. The writer must collect an invalidate acknowledgement from each sharer before entering M.

Up nextMESI States and the Single-Writer Invariant

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