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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
    • Cache Coherence for the Architect
      • MESI States and the Single-Writer Invariant
      • Misses, Upgrades, and Evictions
      • Variants and Scaling: MOESI, MESIF, Snoop, Directory
      • ACE and CHI: An Honest Introduction
      • Sharing Costs and Coherence Triage
    • Memory Ordering Models
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Cache Coherence for the Architect
  1. Topics
  2. Computer Architecture
  3. Coherency and Memory Ordering
  4. Cache Coherence for the Architect
  5. ACE and CHI: An Honest Introduction

Computer Architecture · All levels

ACE and CHI: An Honest Introduction

ACE channels and CHI transactions, and why CHI is not simply a newer ACE.

On this page

    ACE wires

    ACE extends AXI with three snoop channels. AC carries snoop requests, CR returns snoop responses, and CD moves snoop data.

    Shareability travels in AxDOMAIN. Barriers and DVM messages carry scope for ordering.

    Opcode

    One-line intent

    ReadShared

    Fetch a shareable copy

    ReadUnique

    Fetch with others invalidated, for a line about to be written

    MakeUnique

    Invalidate other copies without a data transfer

    CleanUnique

    Clean dirty data out while keeping a unique copy

    Evict / WriteBack

    Write a dirty line back and drop it

    CHI wires

    CHI connects requesters, home nodes, and subordinates (RN, HN, SN). Traffic uses four message classes: REQ, RSP, DAT, and SNP.

    The home node holds the directory and sends targeted snoops. Collided requests reissue through retry, and the requester closes read-write transactions with CompAck.

    CHI is a different decoupled-transaction protocol, not a newer ACE. Packet flits, separate message classes, and per-class resources replace the shared AXI-style channels.

    Axis

    ACE

    CHI

    Fabric

    AXI channels plus snoop broadcast or filter

    RN-HN-SN packet fabric

    Coherence point

    Snoop exchange between peers

    Directory at the home node

    Flow control

    Valid/ready handshake per channel

    Valid/ready per class plus link credits and retry

    Ordering

    Barriers and DVM scope

    Ordering scopes, QoS, and CompAck

    Mapping checklist

    The on-call question here is a migration that gains throughput but surprises ordering. Audit attributes first and bandwidth second.

    ACE side

    CHI side

    Check

    AxDOMAIN plus shareability

    CHI domain and shareability attributes

    No silent scope downgrade at the bridge

    Barrier and DVM behavior

    Ordering scope plus QoS

    Completion still fenced under load

    All CR responses collected

    CompAck plus RSP sequencing

    No early completion signal

    Channel queue sizes

    Credit pool plus retry depth

    Recompute by Little's law, never copy sizes

    Two worked sizings

    Directories replace broadcast probes with targeted ones. Assume 16 requesters and a line shared by 8.

    Diagram
    Write to a line with 8 sharers, 16 requesters:
      broadcast probes = 16 - 1 = 15
      directory probes = 8 targeted, plus 8 acks
      probes saved = 15 - 8 = 7, about 47 percent (7 / 15 = 0.467)

    Credit pools cover the bandwidth-delay product. Assume 32 GB/s and a 20 ns round trip.

    Diagram
    Credit depth for one class, 64 B credits:
      bytes  = 32e9 B/s x 20e-9 s = 640 B
      credits = 640 / 64 = 10; size 12 to 16 for margin

    Common mistakes

    Common pitfall

    Calling CHI a newer ACE. Bridges that map channels one-to-one drop shareability scope or complete barriers early, which passes idle tests and fails under DMA pressure.

    Interview

    Likely probe: the first three audits on an ACE-to-CHI migration. Answer: attribute mapping completeness, barrier completion under credit pressure, and monitor agreement on completion at every boundary.

    Check yourself A barrier passes idle but completes early under DMA load. Which mapping is suspect?

    The barrier-to-ordering-scope mapping or the completion rule. The bridge acknowledged completion before all ordered transactions drained, which credit pressure exposed.

    Check yourself Transaction progress stalls although datapath bandwidth is free. What do you check before blaming ownership conflicts?

    Credit return and retry counters. Control/credit lag stalls issue even when data paths sit idle.

    Related topics

    • Protocols course

    • Memory consistency models

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    See also

    • MESI States and the Single-Writer Invariant
    • Misses, Upgrades, and Evictions