Memory ordering decides when one core observes another core's loads and stores. Coherence keeps values aligned per location, while ordering controls the visible sequence across locations.
Litmus pattern | Question it answers |
|---|---|
Store buffering (SB) | Can two cores each miss the other's store? |
Message passing (MP) | Can a flag arrive before the data it guards? |
Load buffering (LB) | Can two cores each read the other's later store early? |
Causality (WRC) and independent reads (IRIW) | Do all cores agree on one global store order? |
Lesson | What it covers |
|---|---|
Guarantee tables for each model, and why coherence is not consistency. | |
Store buffers, forwarding, queues and speculation, with a runnable buffer model. | |
Fence taxonomy, publication placement and a worked fence cost. | |
Reading litmus, proving outcomes by enumeration, and fencing real primitives. |
Ordering, not coherence. The reader can see the flag before the data (the MP weak outcome). A release store with an acquire load, or a full fence on each side, restores the intended order.