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Computer Architecture · All levels

Performance Analysis

Senior architecture playbook for converting traces and counters into bottleneck hypotheses, roofline-guided tradeoffs, and production tuning decisions.

Section goal

Find and remove throughput and latency bottlenecks with measurable gains and bounded regression risk.

Mechanism to narrate

  • Start from a business workload and measurable KPI before opening tools.

  • Separate symptom metrics from root-cause mechanisms across compute, memory, and interconnect.

  • Every optimization must include an acceptance criterion and regression guardrail.

Senior course bar for this section

  • Every topic should end with an architecture decision, not only concept recall.

  • Every fix should state expected metric movement and likely regression surface.

  • Every open assumption should have an owner, tag, and review date.

  • Every recurring issue should become a methodology guardrail or checklist item.

  1. performance-counters/ — Performance Counters and Telemetry

  2. bottleneck-analysis/ — Bottleneck Analysis Framework

  3. roofline-thinking/ — Roofline Thinking for SoC Tradeoffs

  4. workload-tuning/ — Workload-Aware Tuning and Guardrails

Related topics

Key takeaways

  • Senior performance ownership means reproducible analysis and release-grade decision quality.

Section deep dive

PMU evidence beats intuition for architecture decisions.

Concept diagram

diagram
TOP-DOWN PERFORMANCE METHOD

Total cycles
 ├─ Retiring useful work
 ├─ Frontend bound
 ├─ Bad speculation
 ├─ Backend core bound
 └─ Backend memory bound

Only after classification should you propose cache, branch, pipeline, or NoC changes.

Metric graph

diagram
ROOFLINE SKETCH

Performance
  ^
  |                     compute roof
  |-------------------------------
  |                   /
  |                 /
  |               /   ● workload A (compute-bound)
  |             /
  |   ● workload B (memory-bound)
  +---------------------------------> arithmetic intensity
        memory bandwidth slope

Metrics and artifacts

  • PMU event sets

  • roofline chart

  • top-down stall breakdown

  • workload sensitivity matrix

Mini case study

Team proposed wider SIMD but roofline showed memory-bound kernel — bandwidth upgrade and locality fix delivered 2× speedup at lower area cost.

Debug branches

  • If counters disagree with sim, align workload and warmup.

  • If bottleneck unclear, use top-down method before microarch tweaks.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

  • Connect every architecture claim to a workload and measurable metric.

  • State verification and PPA impact before proposing design changes.

Common pitfalls

  • Feature-driven design without MPKI/IPC/bandwidth evidence.

  • Ignoring coherency and NoC traffic in cache and accelerator sizing.

Practice this lesson