Computer Architecture

Pipeline Fundamentals

3

14

How pipelines, branches, and out-of-order issue set IPC.

Memory Hierarchy

3

15

Caches, bandwidth, and virtual memory from AMAT to TLB reach.

NoC Interconnect

1

6

Topology, routing, flow control, and QoS for on-chip networks.

Coherency and Ordering

2

9

MESI sharing costs and what each memory model guarantees.

Performance Analysis

2

9

Counters, top-down triage, roofline bounds, and tuning moves.

Accelerator Architectures

1

6

When accelerators win, dataflow contracts, locality, and integration.

SoC Architecture Tradeoffs

2

9

PPA budgets, power and energy, floorplans, and signoff gates.

Interview Prep

2

14

Whiteboard method, worked scenarios, and a deduplicated Q and A bank.

1-2

Pipeline Throughput, Branch Prediction and Fetch

Derive CPI from a stall breakdown.

3-5

Caches, Memory Bandwidth and Latency

Size a cache level with AMAT and MPKI.

6-8

Performance Method, Roofline and Tuning

Place a kernel on its roofline.

9-11

Cache Coherence for the Architect, Memory Ordering Models

Trace a sharing miss to its traffic.

12-14

Interview Method and Worked Scenarios, Architecture Interview Q and A Bank

Close a whiteboard answer with numbers.

1

Pipeline Throughput, Branch Prediction and Fetch, Out-of-Order Superscalar Execution

Attribute an IPC gap to frontend, backend, or memory.

2

Caches, Memory Bandwidth and Latency, Virtual Memory and the TLB

Triage a miss storm by capacity, conflict, or translation.

3

On-Chip Networks, Cache Coherence for the Architect, Memory Ordering Models

Separate fabric stalls from sharing costs.

4

Performance Method, Roofline and Tuning

Run one-experiment triage on a live workload.

5

Accelerators for the Architect, PPA at System Level, Power and Energy for the Architect

Defend an offload and its budget impact.

6

Interview Method and Worked Scenarios, Architecture Interview Q and A Bank

Present a full metric to validation story.