Computer Architecture for Chip Engineers

Who this is for

Target audience: SoC architects, performance engineers, RTL leads, and senior designers making microarchitecture and system tradeoffs (3–15+ YOE). You need basic RTL literacy — this course trains measurable architecture judgment : IPC, bandwidth, coherency, and how decisions propagate to PD, power, and verification.

• CPU and accelerator architects defining pipeline and memory hierarchy

• Performance engineers closing workload gaps with PMU and trace evidence

• RTL leads negotiating PPA budgets with architecture and PD owners

• Interview prep for architecture / performance / SoC design roles

How this differs from RTL course content

• RTL Design (/topics/rtl) — how to write correct, synthesizable logic.

• This course — why the microarchitecture is shaped this way and how to debug performance at system level.

• Physical Design (/topics/pd) — how to close implementation; this course explains what architecture handed PD.

• SoC Integration (/topics/soc) — chip assembly; this course covers the architecture inside the blocks.

Related topics

• RTL Design course

• SoC Integration (outline)

• Physical Design course

• PD-aware RTL

Architecture analysis flow

Workload / benchmark
    │
    ▼
 Metrics (IPC, CPI, MPKI, bandwidth, latency, stalls)
    │
    ▼
 Mechanism (pipeline, cache, NoC, coherency, memory)
    │
    ▼
 Hypothesis → experiment (PMU, trace, sim, FPGA)
    │
    ▼
 Design change (microarch, system, RTL structure)
    │
    ▼
 Validation (regression workloads, PPA, verification impact)

Visual map of the course

PRODUCT WORKLOAD
                          │
          ┌───────────────┼────────────────┐
          ▼               ▼                ▼
      CPU PIPELINE   MEMORY HIERARCHY   ACCELERATOR
          │               │                │
          └───────┬───────┴───────┬────────┘
                  ▼               ▼
             NoC / FABRIC     COHERENCY
                  │               │
                  └───────┬───────┘
                          ▼
              PERFORMANCE + PPA TRADEOFF
                          │
                          ▼
             RTL / DV / PD / SOFTWARE ACTION

Read every section through this map. A cache choice changes NoC traffic; a NoC choice changes latency tails; a coherency choice changes software and verification; every choice has power, area, timing, and validation cost.

Example graph-driven decision

Problem: workload IPC regressed 12%

Metric stack:
  frontend stalls  ███████       14%
  branch stalls    █████         10%
  memory stalls    ██████████████████████  44%
  NoC/QoS stalls   █████████     18%
  retire bound     ████          8%

Decision:
  Do not widen decode first. Investigate memory hierarchy, NoC arbitration,
  and coherency traffic because those bars dominate the lost cycles.

8-week study plan (45 min/day)

1. Week 1: how-to-use + pipeline fundamentals.

2. Week 2: memory hierarchy + cache debug patterns.

3. Week 3: NoC + flow control + QoS.

4. Week 4: coherency + memory ordering.

5. Week 5: performance counters + roofline analysis.

6. Week 6: accelerator architectures + integration.

7. Week 7: SoC PPA tradeoffs + floorplan-aware design.

8. Week 8: interview scenarios + cheatsheet.

Course sections

1. pipeline-fundamentals — stages, hazards, branch prediction

2. memory-hierarchy — caches, replacement, bandwidth

3. noc-interconnect — topology, routing, QoS, deadlock

4. coherency-ordering — MESI, ACE/CHI, memory models

5. performance-analysis — PMU, bottlenecks, roofline

6. accelerator-architectures — GPU/NPU/DSA patterns

7. soc-architecture-tradeoffs — PPA, floorplan, signoff

8. interview-prep — whiteboard framework + scenarios

9. cheatsheet — one-page architecture patterns

Key takeaways

• Architecture interviews reward metric-first reasoning, not buzzwords.

• Every design choice has a measurable stall, bandwidth, or coherency story.

• Connect microarchitecture decisions to PD, power, and verification early.

Common pitfalls

• Optimizing IPC without naming the workload — meaningless.

• Adding cache capacity without analyzing MPKI and bandwidth — expensive guess.

• Ignoring coherency traffic when sizing NoC — bandwidth surprise at integration.

Section deep dive

Computer architecture decisions must be tied to workload metrics and silicon constraints.

Concept diagram

ARCHITECTURE DECISION LOOP

workload → metric → bottleneck mechanism → experiment → design option → validation

Metric graph

METRIC TREND

bad run  ██████████
base     ██████████████
target   ████████████████████

Metrics and artifacts

• IPC/CPI

• latency

• bandwidth

• power

• area

• verification risk

Mini case study

A senior architecture review converts a vague performance issue into a metric, a mechanism, an experiment, and a bounded design choice.

Debug branches

• If the metric is not workload-specific, do not accept the conclusion.

• If the fix has no PPA and verification statement, the review is incomplete.

Senior review question

Ask: what single metric would prove this concept is working or failing on your workload?

Key takeaways

• Connect every architecture claim to a workload and measurable metric.

• State verification and PPA impact before proposing design changes.

Common pitfalls

• Feature-driven design without MPKI/IPC/bandwidth evidence.

• Ignoring coherency and NoC traffic in cache and accelerator sizing.