Pipeline Throughput · arch

Computer Architecture · All levels

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5lessons

A five-stage pipeline overlaps fetch, decode, execute, memory and writeback. Once the pipe is full, one instruction completes per cycle while each takes five cycles to emerge.

Five-stage pipeline with registers between stages.

The classic five stages with a pipeline register between each pair. Each register carries data plus control.

Stage	Work	Hands to the next stage
IF	Fetch the next instruction at PC	Instruction word and PC
ID	Decode and read source registers	Operands, immediates and control
EX	ALU work and branch compare	Result or target plus control
MEM	Load and store to memory	Loaded data or store status
WB	Write the result to the register file	Retired instruction, nothing further

Lesson	Covers
The five-stage datapath	What each stage holds and how valid and kill stay aligned.
Stage depth and clock period	Splitting delay across stages and the frequency-latency trade.
CPI and speedup arithmetic	CPI stacks and the IPC-times-frequency test for any change.
Hazard classes	Structural, data and control hazards with stall arithmetic.
Forwarding and stalls	Bypass paths, youngest-wins select and the load-use bubble.

Check yourself Frequency rises 7 percent after a repartition while IPC falls 6 percent. Did throughput improve?

Barely. Throughput scales with 1.07 x 0.94 = 1.01, about a 1 percent gain. The CPI lesson shows the full check.

Up nextThe Five-Stage Datapath

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Stage

Work

Hands to the next stage

Fetch the next instruction at PC

Instruction word and PC

Decode and read source registers

Operands, immediates and control

ALU work and branch compare

Result or target plus control

MEM

Load and store to memory

Loaded data or store status

Write the result to the register file

Retired instruction, nothing further

Lesson

Covers

The five-stage datapath

What each stage holds and how valid and kill stay aligned.

Stage depth and clock period

Splitting delay across stages and the frequency-latency trade.

CPI and speedup arithmetic

CPI stacks and the IPC-times-frequency test for any change.

Hazard classes

Structural, data and control hazards with stall arithmetic.

Forwarding and stalls

Bypass paths, youngest-wins select and the load-use bubble.