Out-of-Order Superscalar Execution · arch

Computer Architecture · All levels

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A superscalar core issues several instructions per cycle. Out-of-order execution lets independent instructions pass stalled ones, while in-order commit keeps precise state.

Flow of instructions through an out-of-order superscalar core.

Instructions enter in order, execute when ready, and leave in order through the reorder buffer.

Lesson	What it covers
Superscalar issue width	Issue width as the IPC ceiling and utilization as the result.
In-order versus out-of-order	Stalling on dependencies versus working around them.
Register renaming	Removing false dependencies with physical registers.
Reorder buffer and commit	In-order commit, speculation recovery and window sizing.
Why IPC saturates	Dependencies, memory and branches as the three caps.

Check yourself A 4-wide core sustains IPC 1.2. What fraction of issue slots do useful work?

1.2 divided by 4 is 0.30, so 30 percent of slots retire useful instructions and the rest are stalls or waste.

Up nextSuperscalar Issue Width

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