An N-wide core fetches, issues and can retire up to N instructions per cycle. Peak IPC therefore equals N, and peak throughput equals N times the clock frequency.
The ceiling is structural. No schedule exceeds it, however independent the code.
Issue width | Peak IPC | Peak throughput at 3 GHz |
|---|---|---|
2-wide | 2 | 6 GIPS |
4-wide | 4 | 12 GIPS |
8-wide | 8 | 24 GIPS |
Sustained IPC equals width times the fraction of slots that issue useful work. Dependencies, cache misses and mispredicts leave the remaining slots empty.
The worked example below uses stated example parameters, not measured silicon.
4-wide core, 3 GHz clock, 60 percent slot utilization (stated example)
ideal IPC = width = 4
sustained IPC = 4 x 0.60 = 2.4
peak throughput = 4 x 3.0 GHz = 12.0 GIPS
sustained throughput = 2.4 x 3.0 GHz = 7.2 GIPSDoubling width doubles the ceiling but rarely doubles sustained IPC. The wider machine exposes the same dependency chains to more slots that still cannot fill.
Suppose a workload sustains 70 percent utilization on a 2-wide core and 48 percent on a 4-wide core. Then IPC is 1.4 versus 1.92, a gain of 1.37x for twice the issue hardware.
stated utilizations: 2-wide 70 percent, 4-wide 48 percent
IPC 2-wide = 2 x 0.70 = 1.40
IPC 4-wide = 4 x 0.48 = 1.92
speedup = 1.92 / 1.40 = 1.37 (37 percent, not 2x)1.4 times 3.0 GHz is 4.2 GIPS, against a 6 GIPS peak.
Any two: stalled issue on data dependencies, drained window after a mispredict, load-miss replay pressure, or structural conflicts on too few functional units.