The memory hierarchy trades area and power for access latency and delivered bandwidth. Caches set hit latency and miss rate while the DRAM path and page tables set sustained bandwidth and translation cost.
Topic | Lessons | Description | Time |
|---|---|---|---|
6 | How sets, ways and address decode set hit latency, miss rate and cache area. | 50 min | |
5 | Peak versus delivered memory bandwidth, Little's law, DRAM scheduling, prefetching and debug method. | 40 min | |
4 | Virtual addresses, page tables, TLB reach, huge pages, and how translation meets caches. | 30 min |
Runtime follows hit latency plus miss rate times miss penalty, minus overlap: a more associative cache can add hit cycles that cancel the miss saving. The Caches topic covers AMAT and memory-level parallelism.