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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Computer Architecture
  1. Topics
  2. Computer Architecture
  3. Workload Taxonomy for Architects

Computer Architecture · All levels

Workload Taxonomy for Architects

Six workload classes, the structure each stresses, and the metric that exposes the bottleneck.

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    Classify the workload before touching the design. Each class below names its mechanism in one line and the metric that exposes it.

    The six classes

    Workload

    Structure it stresses

    Metric that exposes it

    Branchy control flow

    Fetch width, predictor tables, and I-cache hold the mechanism.

    Branch mispredict MPKI and frontend stall share.

    Pointer chase, irregular

    D-cache, TLB, LLC, and DRAM serve each dependent miss.

    MPKI per level, TLB MPKI, and AMAT.

    Streaming, sequential

    Prefetcher, NoC, and DRAM bandwidth carry the stream.

    Delivered bandwidth, coverage, and MLP.

    Producer-consumer sharing

    Coherency protocol, line size, and layout set the cost.

    Invalidations and snoop or directory traffic.

    Accelerator offload

    SRAM tile, DMA engine, and launch path bound the win.

    Utilization, DMA bandwidth, and launch cost.

    Latency-critical service

    Queues, arbitration, and QoS classes guard the tail.

    p99 latency and tail share under load.

    How to use the map

    Match the workload to one row, then measure that row's metric first. If the metric is flat, the bottleneck sits in a different row.

    Related topics

    • Course Hub

    • Metrics Reference

    • Performance Method

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    See also

    • Computer Architecture Cheatsheet
    • Pipeline Fundamentals
    • Memory Hierarchy