Each entry states its assumptions and units. Every number below divides evenly by hand.
CPI is cycles per instruction and IPC is its inverse. Both describe one named workload, never a core in the abstract.
A core retires 3 instructions every 2 cycles.
IPC = 3 instr / 2 cycles = 1.5 instr/cycle
CPI = 1 / IPC = 1 / 1.5 = 0.67 cycles/instrSpeedup is bounded by the fraction that does not improve. P is the share of runtime that speeds up by S.
P = 0.60 of runtime speeds up by S = 4.
Speedup = 1 / ((1 - 0.60) + 0.60 / 4)
= 1 / (0.40 + 0.15)
= 1 / 0.55 = 1.82Average memory access time adds hit time to miss rate times miss penalty. Use the miss rate as a fraction, not a percent.
Hit time 1 cycle, miss rate 5%, miss penalty 100 cycles.
AMAT = 1 + 0.05 x 100 = 1 + 5 = 6 cyclesMPKI is misses per thousand instructions at one cache level. Each miss costs its penalty in stalled cycles.
MPKI 10 at the LLC, miss penalty 100 cycles.
Misses per instr = 10 / 1000 = 0.01
CPI addition = 0.01 x 100 = 1.0 cycle/instrConcurrency equals throughput times latency. It sizes queues, MSHRs, and outstanding requests.
A link moves 64-byte lines at 10 GB/s, average latency 100 ns.
Lines per second = 10e9 / 64 = 156,250,000
Outstanding = 156,250,000 x 100e-9 = 15.625
So about 16 outstanding lines hide the latency.Arithmetic intensity is operations per byte moved from memory. It converts a bandwidth limit into a compute ceiling.
A kernel does 1 FLOP per 4 bytes moved.
Intensity = 1 / 4 = 0.25 FLOP/byte
Ceiling at 100 GB/s = 100e9 x 0.25 = 25 GFLOP/sSustained performance stays under both the compute peak and the bandwidth times intensity product. The lower roof binds.
Peak 1000 GFLOP/s, bandwidth 200 GB/s, intensity 2 FLOP/byte.
Memory ceiling = 200 x 2 = 400 GFLOP/s
Perf <= min(1000, 400) = 400 GFLOP/s, memory boundSwitching power scales with capacitance, the square of voltage, and frequency. Voltage moves the result fastest.
C = 2 nF, V = 0.8 V, f = 2 GHz.
P = C x V^2 x f = 2e-9 x 0.64 x 2e9
= 2 x 0.64 x 2 = 2.56 W