AMAT

Average memory access time: hit time plus miss rate times miss penalty. Caches

Arithmetic intensity

Operations per byte moved from memory. Higher values favor compute. Roofline and Tuning

Associativity

Number of places a block can sit in a set. More ways cut conflict misses. Caches

Branch mispredict penalty

Cycles lost flushing and refilling fetch after a wrong prediction. Branch Prediction and Fetch

Credit flow control

Downstream buffer credits gate NoC sends, so no packet is dropped. On-Chip Networks

Directory protocol

A sharer list tracks cached copies and filters coherence probes. Cache Coherence

DMA

Direct memory access moves tiles without the core. Bandwidth and launch cost bound it. Accelerators

DVFS

Dynamic voltage and frequency scaling trades speed for energy. Voltage dominates. Power and Energy

Exclusive state

The MESI state holding the only clean copy, so a write needs no bus probe. Cache Coherence

False sharing

Independent data in one line causing coherence traffic without true sharing. Cache Coherence

Fence

An ordering instruction that restores guarantees the hardware model omits. Memory Ordering

IPC and CPI

Instructions per cycle and its inverse, always tied to a named workload. Pipeline Throughput

Leakage power

Static drain from off transistors. It grows with temperature and small geometries. Power and Energy

Litmus test

A tiny concurrent program that exposes what an ordering model allows. Memory Ordering

MESI

Modified, Exclusive, Shared, Invalid: states keeping one writer across private caches. Cache Coherence

MLP

Memory-level parallelism: outstanding misses overlapping one stall. MSHRs cap it. Memory Bandwidth

MPKI

Misses per thousand instructions at one cache level. Performance Method

MSHR

Miss status holding register tracking each outstanding miss. Count limits MLP. Caches

NoC

Network on chip moving packets between cores, caches, and memory. On-Chip Networks

Out-of-order execution

Issuing ready instructions past stalled ones via renaming and a reorder buffer. Out-of-Order Execution

Prefetcher

Hardware predicting future lines to cut compulsory and capacity misses. It can pollute. Memory Bandwidth

QoS

Quality of service protecting latency-critical traffic under contention. On-Chip Networks

Roofline model

Performance ceiling from compute peak and bandwidth times intensity. Roofline and Tuning

Row buffer

DRAM row held open for fast hits. Hit rate sets delivered bandwidth. Memory Bandwidth

TLB

Translation lookaside buffer caching page mappings. Reach sets miss cost. Virtual Memory