Computer Architecture · All levels
Architecture Glossary
Quick definitions for pipeline, memory, NoC, coherency, and performance terms used across the course.
Terms you must own
IPC — instructions retired per cycle on a named workload.
MPKI — cache misses per thousand instructions.
MSHR — miss status holding register; limits memory-level parallelism.
Roofline — binds compute peak and memory bandwidth against arithmetic intensity.
MESI/MOESI — cache coherence states governing sharing and ownership.
VC — virtual channel in NoCs; isolates traffic classes and helps avoid protocol deadlock.
QoS — quality of service; protects latency-critical traffic under contention.
False sharing — independent data in the same cache line causing coherence traffic.
Arithmetic intensity — operations per byte moved from memory.
Tail latency — high-percentile latency, often more important than average.
Architecture deep dive
Computer architecture decisions must be tied to workload metrics and silicon constraints.
Concept diagram
ARCHITECTURE DECISION LOOP
workload → metric → bottleneck mechanism → experiment → design option → validationMetric graph
METRIC TREND
bad run ██████████
base ██████████████
target ████████████████████Metrics and artifacts
IPC/CPI
latency
bandwidth
power
area
verification risk
Mini case study
A senior architecture review converts a vague performance issue into a metric, a mechanism, an experiment, and a bounded design choice.
Debug branches
If the metric is not workload-specific, do not accept the conclusion.
If the fix has no PPA and verification statement, the review is incomplete.
Senior review question
Ask: what single metric would prove this concept is working or failing on your workload?
Key takeaways
Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.
Common pitfalls
Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.