Caches · arch | DenseChip

Computer Architecture · All levels

6topics
6lessons

A cache trades hit latency against miss rate under area and power caps. Every lesson below derives its numbers from stated formulas and small runnable models.

Organization	Compare cost	Miss behavior	When it fits
Direct-mapped	One tag compare, fastest hit	Conflict misses on any alias	Tiny structures or historical baselines
Set-associative	One compare per way, slower hit	Fewer conflict misses as ways grow	Most L1, L2 and LLC levels
Fully associative	A compare per line, slowest and hottest	No conflict misses, only capacity and compulsory	Small buffers such as TLBs
Victim cache	One small fully associative side buffer	Catches conflict evictions before they leave	Direct-mapped or low-way L1 designs

Lesson	What it covers
Address decode and the access path	Index, tag and offset split, and the hit and miss path.
Associativity and the three Cs	Ways, miss classes, and measured conflict misses.
AMAT, MPKI and memory-level parallelism	Average access time, correct MPKI use, and overlap.
Replacement and thrashing	Victim choice, Belady bound, and insertion fixes.
Write policies and coherence hooks	Write hit and miss options, traffic, and directory costs.
Sizing a level and triaging misses	A scored trade study and the MPKI split method.

Check yourself A larger cache raises the hit rate but slows the clock on hits. Which single metric decides whether it helped?

Average memory access time. It combines hit latency with miss rate times miss penalty, so it prices both sides of the trade.

Up nextAddress Decode and the Access Path

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Organization

Compare cost

Miss behavior

When it fits

Direct-mapped

One tag compare, fastest hit

Conflict misses on any alias

Tiny structures or historical baselines

Set-associative

One compare per way, slower hit

Fewer conflict misses as ways grow

Most L1, L2 and LLC levels

Fully associative

A compare per line, slowest and hottest

No conflict misses, only capacity and compulsory

Small buffers such as TLBs

Victim cache

One small fully associative side buffer

Catches conflict evictions before they leave

Direct-mapped or low-way L1 designs

Lesson

What it covers

Address decode and the access path

Index, tag and offset split, and the hit and miss path.

Associativity and the three Cs

Ways, miss classes, and measured conflict misses.

AMAT, MPKI and memory-level parallelism

Average access time, correct MPKI use, and overlap.

Replacement and thrashing

Victim choice, Belady bound, and insertion fixes.

Write policies and coherence hooks

Write hit and miss options, traffic, and directory costs.

Sizing a level and triaging misses

A scored trade study and the MPKI split method.