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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
      • Address Decode and the Access Path
      • Associativity and the Three Cs
      • AMAT, MPKI and Memory-Level Parallelism
      • Replacement and Thrashing
      • Write Policies and Coherence Hooks
      • Sizing a Level and Triaging Misses
    • Memory Bandwidth and Latency
    • Virtual Memory and the TLB
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Caches
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Caches
  5. Sizing a Level and Triaging Misses

Computer Architecture · All levels

Sizing a Level and Triaging Misses

A scored associativity trade study and the MPKI split method for miss regressions.

On this page

    The trade study

    The table below reuses legacy numbers as synthetic inputs, not silicon data. A 12-way pilot lifts the L2 hit rate but slows every L2 hit and raises energy per instruction.

    Net IPC falls on the measured mix. The pilot survives only where latency tolerance beats hit rate, segmented by SKU.

    Metric

    Baseline

    12-way pilot

    Reading

    L2 hit rate

    87.1%

    90.4%

    Plus 3.3 points of hits

    L2 hit latency

    13 cycles

    16 cycles

    Plus 3 cycles on every L2 hit

    LLC MPKI

    11.9

    10.7

    Minus 1.2 misses per kilo-instruction

    Energy per instruction

    1.82 nJ

    1.98 nJ

    Plus 0.16 nJ per instruction

    IPC

    1.46

    1.44

    Minus 0.02, so the pilot loses here

    The MPKI split method

    One method handles every miss regression. Split the MPKI delta into demand, prefetch-evicted and coherence shares before touching any structure.

    1. Freeze counters and windows: confirm the same events and sampling on both sides.

    2. Split the delta: demand misses, prefetch-evicted lines and coherence invalidations.

    3. Normalize and localize: convert with accesses per kilo-instruction, then map hot sets with a pressure heatmap.

    4. Classify: dead-on-fill means pollution or insertion trouble, hot sets mean conflict or policy, flat spread means capacity or workload shift.

    5. Run one bounded experiment and sign off with latency, bandwidth and fairness guards.

    Diagram
    synthetic regression: LLC MPKI 18.4 -> 24.1, delta +5.7
    demand      +3.1 (54.4% of the delta)
    prefetch    +2.2 (38.6% of the delta)
    coherence   +0.4 (7.0% of the delta)
    shares sum to 100.0% up to rounding
    top-42 hot sets hold about 60% of misses with high dead-on-fill share
    verdict: insertion and prefetch admission suspect, not capacity

    Common mistakes

    Common pitfall

    Tuning against one locality microbenchmark and calling it production truth. Require the gain across the portfolio mix and check antagonistic patterns for regressions.

    Interview

    Likely probes: the pilot decision and the first triage step.

    • Higher associativity can lose through slower hits and higher energy: quote AMAT and perf per watt.

    • First step is always counter definitions and windows, never a structure change.

    • Close with telemetry guardrails and a fallback, not one green run.

    Check yourself MPKI rose but hot sets are flat and dead-on-fill is low. What does that suggest?

    Capacity pressure or a workload footprint shift. Neither conflict fixes nor insertion tuning match a flat spread.

    Check yourself The split shows prefetch-evicted lines up 2.2 MPKI. What is the bounded experiment?

    Tighten prefetch admission or depth on a shadow run, and watch demand hits plus p95 latency before any rollout.

    Related topics

    • Performance method

    • Interview method and worked scenarios

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    See also

    • Address Decode and the Access Path
    • Associativity and the Three Cs
    • AMAT, MPKI and Memory-Level Parallelism