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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
      • Address Decode and the Access Path
      • Associativity and the Three Cs
      • AMAT, MPKI and Memory-Level Parallelism
      • Replacement and Thrashing
      • Write Policies and Coherence Hooks
      • Sizing a Level and Triaging Misses
    • Memory Bandwidth and Latency
    • Virtual Memory and the TLB
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Caches
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Caches
  5. Write Policies and Coherence Hooks

Computer Architecture · All levels

Write Policies and Coherence Hooks

Write-through and write-back choices, dirty-line traffic, and directory bit costs.

On this page

    Write hit and miss choices

    Write-through sends every store to the next level at once. Write-back holds stores in the line and pays DRAM traffic once, on a dirty eviction.

    The miss side is independent. Write-allocate fetches the line first, while write-no-allocate sends the store around the cache.

    Combination

    Store traffic

    Fits

    Write-through with no-allocate

    Every store leaves the cache

    Small buffers over slow memories

    Write-through with allocate

    Every store leaves, plus a fill

    Rarely, needs a special reason

    Write-back with allocate

    One line write per dirty eviction

    Most data caches

    Write-back with no-allocate

    Bypass for streaming stores

    Non-temporal or streaming writes

    What write-back costs

    Dirty evictions convert into bandwidth. The product below uses illustrative inputs and converts eviction counts into bytes per second.

    Metadata adds a second tax. Every line carries valid, dirty, tag, replacement and coherence bits whether or not it holds useful data.

    Diagram
    illustrative: LLC evicts 2.0M lines/s, 35% dirty, 64-byte lines
    writeback traffic = 0.35 x 2,000,000 x 64 B = 44,800,000 B/s = 44.8 MB/s
    metadata, illustrative 48-bit addresses: 1-MB cache, 16-way, 64-B lines
    lines = 1048576 / 64 = 16384; sets = 16384 / 16 = 1024
    index = 10 bits; offset = 6 bits; tag = 48 - 10 - 6 = 32 bits
    bits per line = 1 valid + 1 dirty + 32 tag + 4 LRU + 2 MESI = 40
    total = 40 x 16384 = 655,360 bits = 80 KiB, about 7.8% of 1 MB

    Hooks, not protocols

    This topic keeps only the cost side of coherence. Sharer tracking, transient states and ordering rules live in the coherency topic.

    Three hooks cross the boundary. The directory or snoop filter needs bits per line, inclusion choices decide who evicts whom, and eviction of a shared line may need a back-invalidation.

    Hook

    What the cache pays

    Detail lives in

    Sharer tracking

    Directory or filter bits per line

    Cache coherence for the architect

    Inclusion policy

    Back-invalidation traffic on evict

    Cache coherence for the architect

    Writeback ordering

    Fence and drain rules at the boundary

    Memory consistency models

    Common mistakes

    Common pitfall

    Counting write-back as free because hits look clean. The bill arrives at eviction time as bursty DRAM writes, so size the drain path for eviction bursts, not average store rate.

    Interview

    Likely probes: the 2-by-2 grid and the two taxes.

    • Name the standard pairing first: write-back with allocate for data caches.

    • Price write-back with dirty-evict traffic, and metadata with bits per line.

    • Push protocol depth to the coherency topic by name.

    Check yourself A streaming writer fills the cache with lines never read again. Which pairing avoids the fill cost?

    Write-back with no-allocate, or non-temporal bypass. Fetching lines only to overwrite them wastes fills and evictions.

    Check yourself Who owns the Exclusive state and transient states in this course?

    The coherency topic. Here they appear only as two metadata bits per line in the area sum.

    Related topics

    • Cache coherence for the architect

    • DRAM memory course

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    See also

    • Address Decode and the Access Path
    • Associativity and the Three Cs
    • AMAT, MPKI and Memory-Level Parallelism