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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
      • Address Decode and the Access Path
      • Associativity and the Three Cs
      • AMAT, MPKI and Memory-Level Parallelism
      • Replacement and Thrashing
      • Write Policies and Coherence Hooks
      • Sizing a Level and Triaging Misses
    • Memory Bandwidth and Latency
    • Virtual Memory and the TLB
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Caches
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Caches
  5. Replacement and Thrashing

Computer Architecture · All levels

Replacement and Thrashing

Victim choice under pressure, the optimal bound, and insertion fixes for cyclic code.

On this page

    Picking the victim

    Replacement picks the eviction victim when every way of a set is valid. The policy only affects conflict and capacity victims, never compulsory misses.

    True LRU tracks exact age per line. Cheaper approximations trade accuracy for fewer bits and faster decisions.

    Policy

    State per set

    Weakness

    True LRU

    Age per line

    Bit cost and update energy grow with ways

    Tree pseudo-LRU

    One bit per tree node

    Skews under bursty reuse, evicts the wrong branch

    Random or not-recently-used

    Almost none

    Evicts hot lines by chance

    Adaptive insertion (BIP, DIP, RRIP)

    Insertion priority plus small counters

    Needs telemetry and a fallback

    When LRU collapses

    A cyclic working set one line larger than the cache defeats LRU completely. Every access evicts a line that is needed again almost immediately.

    Belady optimal replacement sets the bound. It evicts the line used farthest in the future, which needs perfect knowledge and serves only as a reference.

    Diagram
    4-way set, cyclic trace A B C D E repeated twice (10 references)
    LRU: fills A B C D (4 misses), then every reference evicts its own reuse
      LRU misses = 10 of 10
    optimal: fill A B C D (4 misses); E evicts D (used farthest ahead);
      A B C hit; D evicts A (never reused); E hits
      optimal misses = 6 of 10 (A B C D E D)
    gap: 4 avoidable misses per 10 references bound what insertion can win

    Reference

    1-4

    5 (E)

    6-8 (A-C)

    9 (D)

    10 (E)

    LRU

    4 misses

    Miss, evict A

    3 misses

    Miss

    Miss

    Optimal

    4 misses

    Miss, evict D

    3 hits

    Miss, evict A

    Hit

    Insertion fixes

    Insertion policy decides where a new line lands in the age order. Bimodal insertion usually places newcomers as almost-evictable, so streaming fills drain without flushing hot lines.

    Reuse distance guides the choice. A histogram of distances past the associativity marks thrash, and dead-on-fill lines confirm pollution rather than a capacity shortfall.

    Fix

    Idea

    Watch out for

    Bimodal insertion

    Most fills insert near LRU, a few near MRU

    Too few MRU inserts starve real reuse

    Dynamic insertion

    Set duel picks LRU or bimodal per phase

    Duel sets must mirror the workload

    Re-reference interval prediction

    Two-bit priority per line, hit resets it

    Counter width and scan order need review

    Common mistakes

    Common pitfall

    Growing the cache to fix a policy thrash buys nothing when the pattern is cyclic. The reuse-distance histogram shows the signature, and insertion fixes it at fixed size.

    Interview

    Likely probes: pseudo-LRU failure modes and the thrash proof.

    • Mixed streaming plus bursty reuse breaks age approximations first.

    • Quote the LRU-versus-optimal gap on a short cyclic trace.

    • Demand staged rollout with fairness monitors for any adaptive policy.

    Check yourself Reuse distances cluster just above the associativity. Bigger cache or new policy?

    New policy. The lines almost fit, so insertion keeps the reusable fraction without new SRAM.

    Check yourself Prefetch fills show high dead-on-fill share. What does that implicate?

    Prefetch admission, not replacement. Dead arrivals pollute regardless of victim choice.

    Related topics

    • Performance method

    • Interview method and worked scenarios

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    See also

    • Address Decode and the Access Path
    • Associativity and the Three Cs
    • Sizing a Level and Triaging Misses