Uncut logic with total delay D needs a period near D plus register overhead. Cut into S balanced stages, the period falls toward D/S plus one register delay.
The slowest stage sets the clock. Uneven stages waste the gain, so balance matters more than count.
Each added stage rank adds area, power and clock load. Latency in cycles grows by construction, and latency in nanoseconds grows slightly from register overhead.
Stages S | Clock period (D = 6 ns, t_reg = 0.3 ns) | Frequency | Latency |
|---|---|---|---|
1 | 6.3 ns | 159 MHz | 6.3 ns |
2 | 3.3 ns | 303 MHz | 6.6 ns |
3 | 2.3 ns | 435 MHz | 6.9 ns |
6 | 1.3 ns | 769 MHz | 7.8 ns |
Tclk = D / S + t_reg, with D = 6.0 ns and t_reg = 0.3 ns
S = 1: 6.0 / 1 + 0.3 = 6.3 ns -> f = 1 / 6.3 ns = 159 MHz, latency = 1 x 6.3 = 6.3 ns
S = 2: 6.0 / 2 + 0.3 = 3.3 ns -> f = 1 / 3.3 ns = 303 MHz, latency = 2 x 3.3 = 6.6 ns
S = 3: 6.0 / 3 + 0.3 = 2.3 ns -> f = 1 / 2.3 ns = 435 MHz, latency = 3 x 2.3 = 6.9 ns
S = 6: 6.0 / 6 + 0.3 = 1.3 ns -> f = 1 / 1.3 ns = 769 MHz, latency = 6 x 1.3 = 7.8 nsPipelining raises throughput for streams of items. It does not hide latency: each item still takes S cycles, and feedback loops feel every added cycle.
Deeper stages expose more bubbles on every stall and lengthen branch recovery. Fetch bandwidth and hazard control must be rebalanced with each split.
Extra flops add clock power with no work attached. A split needs an IPC-times-frequency gain at fixed power, shown in the next lesson.
T = 4.8/4 + 0.2 = 1.4 ns, so about 714 MHz. Latency = 4 x 1.4 = 5.6 ns, longer than the unpipelined 5.0 ns but with about 3.6 times the results per ns (the ideal 4x minus register overhead).
The slow stage sets the clock for all stages. The fix is rebalancing work across the boundary, not adding more stages.