What lives in each stage

Each stage owns one job. Fetch produces an instruction word, decode produces operands, execute produces a result, memory produces loaded data, and writeback retires it.

Stages communicate only through pipeline registers. No stage reaches into another stage directly.

Registers carry data plus control

Control travels with its instruction. A MemRead bit in ID/EX belongs to the instruction in that register, not to the stage.

This pairing is what makes stalls and flushes local decisions. Each register can be held or cleared without touching the others.

Valid and kill alignment

A stall freezes the PC and IF/ID and injects a bubble into ID/EX. The bubble is a register with control bits cleared, so it retires as a no-op.

A flush clears the wrong-path registers and gates side effects. A killed store must never write memory and a killed writeback must never write the register file.

• Stall: hold PC and IF/ID, inject a bubble into ID/EX.

• Flush: clear IF/ID and ID/EX on a taken branch, gate memory and register writes.

• Bubble: valid 0 with control 0, safe to retire.

Testbench

A five-deep valid pipeline with kill, plus a testbench that checks steady-state count, five-cycle latency and kill clearing.

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module pipe_valid (
  input  logic clk,
  input  logic rst_n,
  input  logic in_valid,
  input  logic kill,
  output logic out_valid
);
  logic [4:0] v;
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) v <= 5'b0;
    else begin
      v[0] <= in_valid & ~kill;
      v[1] <= v[0] & ~kill;
      v[2] <= v[1] & ~kill;
      v[3] <= v[2] & ~kill;
      v[4] <= v[3] & ~kill;
    end
  end
  assign out_valid = v[4];
endmodule

Related topics

• Pipelining