Computer Architecture · All levels
Architecture Interview Q&A Bank
25 cross-topic senior architecture questions with traps.
Cross-topic Q&A
Answer with metric, mechanism, experiment, and validation.
Workload IPC dropped 15% after cache change — first three checks?
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Q: Workload IPC dropped 15% after cache change — first three checks?
A:
MPKI by level, L2 bandwidth, stall breakdown (frontend/backend/memory).
FOLLOW-UP TRAP: Assume larger cache always helps.NoC deadlock in simulation — what do you ask first?
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Q: NoC deadlock in simulation — what do you ask first?
A:
Topology, routing algorithm, VC count, credit loop, QoS starvation.
FOLLOW-UP TRAP: Add bandwidth without root cause.MESI vs MOESI tradeoff?
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Q: MESI vs MOESI tradeoff?
A:
MOESI allows shared dirty in cache — reduces off-chip traffic at coherency complexity cost.
FOLLOW-UP TRAP: Name states without traffic story.When add another cache level?
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Q: When add another cache level?
A:
When MPKI × miss penalty × frequency justifies area/power and access latency budget.
FOLLOW-UP TRAP: More levels always better.Branch predictor wrong — symptom?
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Q: Branch predictor wrong — symptom?
A:
Frontend bubbles, fetch/decode stall increase, IPC drop on branch-heavy workload.
FOLLOW-UP TRAP: Only mention mispredict rate without pipeline impact.Accelerator starved — debug order?
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Q: Accelerator starved — debug order?
A:
DMA bandwidth, memory contention, kernel launch overhead, coherency invalidation rate.
FOLLOW-UP TRAP: Clock the accelerator faster first.Roofline says memory-bound — fix?
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Q: Roofline says memory-bound — fix?
A:
Improve locality, prefetch, bandwidth, or reduce arithmetic intensity requirement.
FOLLOW-UP TRAP: Wider issue width.ACE vs CHI at high level?
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Q: ACE vs CHI at high level?
A:
Both support coherent interconnect; CHI is newer generation with different channel/message model — know your SoC IP.
FOLLOW-UP TRAP: Treat as interchangeable buzzwords.Out-of-order vs in-order for embedded?
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Q: Out-of-order vs in-order for embedded?
A:
Trade IPC vs power/area/verification — cite workload and real-time determinism needs.
FOLLOW-UP TRAP: OOO always wins.Memory ordering bug symptom?
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Q: Memory ordering bug symptom?
A:
Rare SW failures, litmus test failures, only on weak ordering cores.
FOLLOW-UP TRAP: Debug as timing issue.PMU shows L3 miss storm — action?
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Q: PMU shows L3 miss storm — action?
A:
Profile working set, page allocation, sharing — consider partition or cache policy.
FOLLOW-UP TRAP: Blindly increase L3 size.Floorplan hurts memory latency — arch response?
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Q: Floorplan hurts memory latency — arch response?
A:
Negotiate macro placement, NoC topology, or accept frequency target change with data.
FOLLOW-UP TRAP: Ignore PD feedback.SMT worth it?
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Q: SMT worth it?
A:
When frontend/backend underutilized and thread mix benefits — costs area, verification, security.
FOLLOW-UP TRAP: Double threads = double IPC.Coherency traffic dominates — fixes?
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Q: Coherency traffic dominates — fixes?
A:
False sharing reduction, directory vs snoop fit, cache line size, data layout.
FOLLOW-UP TRAP: Faster NoC only.Explain TLB miss impact?
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Q: Explain TLB miss impact?
A:
Page walk latency, pipeline stall, may dominate in sparse memory workloads.
FOLLOW-UP TRAP: Ignore MMU in perf analysis.Staff architect vs senior?
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Q: Staff architect vs senior?
A:
Staff owns cross-block budgets, methodology, signoff narrative, and escalation.
FOLLOW-UP TRAP: More technical trivia.NPU integration top risk?
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Q: NPU integration top risk?
A:
Memory bandwidth and coherency with CPU — define ownership and bandwidth contract early.
FOLLOW-UP TRAP: Peak TOPs only.When pipeline deeper?
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Q: When pipeline deeper?
A:
When target frequency and branch predictability support — watch branch and cache penalties.
FOLLOW-UP TRAP: Depth without frequency goal.Chip PPA negotiation example?
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Q: Chip PPA negotiation example?
A:
Present metric dashboard: perf/W, area mm², NoC BW — options with owners.
FOLLOW-UP TRAP: Single metric advocacy.Architecture signoff artifact?
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Q: Architecture signoff artifact?
A:
Workload matrix, perf/Power budgets, verification plan, PD constraints doc.
FOLLOW-UP TRAP: PowerPoint only.Prefetcher harmful case?
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Q: Prefetcher harmful case?
A:
Pollution on streaming or irregular access — measure MPKI and bandwidth.
FOLLOW-UP TRAP: Prefetch always helps.QoS on NoC — why?
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Q: QoS on NoC — why?
A:
Prevent latency-critical traffic starvation by best-effort bulk DMA.
FOLLOW-UP TRAP: Fair arbitration is enough.Cache inclusion policy debate?
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Q: Cache inclusion policy debate?
A:
Inclusion simplifies coherence but can cause eviction traffic — workload dependent.
FOLLOW-UP TRAP: Always inclusive.Explain memory bandwidth roof?
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Q: Explain memory bandwidth roof?
A:
Pin count, DRAM type, NoC links, coherency overhead — numeric estimate.
FOLLOW-UP TRAP: Peak datasheet bandwidth only.Post-silicon perf mismatch?
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Q: Post-silicon perf mismatch?
A:
Workload diff, thermal throttle, binning, PMU setup, trace alignment.
FOLLOW-UP TRAP: Blame RTL immediately.Q&A drill guide
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MECHANISM → METRIC → EXPERIMENT → TRADEOFF → VALIDATIONSketch while answering
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WHITEBOARD ANSWER SHAPE
1. Workload and metric
2. Block diagram
3. Bottleneck hypothesis tree
4. Experiment plan
5. Design options and tradeoffs
6. Validation / regression
If you skip step 1, the rest sounds generic.Key takeaways
Connect every architecture claim to a workload and measurable metric.
State verification and PPA impact before proposing design changes.
Common pitfalls
Feature-driven design without MPKI/IPC/bandwidth evidence.
Ignoring coherency and NoC traffic in cache and accelerator sizing.