Pattern choice starts from kernel structure, reuse behavior, control divergence and software stack limits. Peak throughput numbers rank marketing, not architectures.
Dataflow often dominates clock frequency in effect. Movement and synchronization overhead cap effective throughput long before the MAC array runs out.
Rank kernel structure, reuse distance, branch divergence and compiler maturity first. Then match the pattern to those constraints instead of to peak throughput claims.
Dataflow sets how often operands move and stall on synchronization, which caps utilization. A faster clock on a starved array only idles sooner.
When workload diversity leaves every fixed mode slow on a meaningful deployment slice. Without measured cross-workload benefit, hybrid modes are schedule risk.
A starved accelerator is usually a system problem. Debug order runs DMA bandwidth, memory contention, launch overhead and coherency invalidation before touching the array.
Compute-idle windows diagnose through correlation. Align idle periods with transfer stalls, queue starvation and phase synchronization events on one timeline.
DMA bandwidth delivered, contention from other masters, kernel launch and sync overhead, then coherency invalidation rate. Clocking the array faster is last, not first.
Memory bandwidth and coherency ownership with the CPU cluster. Define the bandwidth contract and the coherence domain early, or peak TOPS never reaches the application.
Correlate idle windows against transfer stalls, queue occupancy and phase barriers. Idleness with empty input queues is starvation, not weak compute.
Accelerator bound from stated parameters
formula: attainable = min(peak_compute, bandwidth x intensity); time = work / attainable
example: 1.2 GFLOP over 48 MB, peak 10 TFLOP/s, usable bandwidth 100 GB/s
result: intensity = 1.2e9 / 48e6 = 25 FLOP per byte; min(10000, 100 x 25) = 2500 GFLOP/s; time = 1.2e9 / 2.5e12 = 0.48 ms, memory-boundBytes moved per useful operation is the locality metric that decides. Hit rate alone can rise while off-chip traffic still dominates end-to-end cost.
Integration signoff covers behavior under concurrency. QoS, coherency latency, power-state transitions, telemetry and error recovery contracts all outrank isolated kernel speed.
Integration check | What it proves | Skipped risk |
|---|---|---|
QoS under concurrency | Deadlines hold with other masters active | Jitter in production traffic |
Coherency latency budget | Shared data arrives in time | Silent serialization stalls |
Power-state transitions | No functional or perf loss across states | First-customer hangs |
Telemetry and error paths | Post-silicon diagnosis is possible | Unroot-causable failures |
Bytes moved per useful operation across hierarchy levels, paired with energy impact. A high SRAM hit rate with heavy refill churn is still a locality failure.
When the workload tolerates explicit synchronization and measurements show clear bandwidth or latency wins. Default coherence without traffic analysis buys complexity for nothing.
When platform contracts fail under concurrency, power transitions or isolation checks. Fast standalone kernels never excuse a broken system contract.
A full-system re-profile naming the next dominant bottleneck with updated guardrails. One landed optimization never closes the project.