Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
    • Interview Method and Worked Scenarios
    • Architecture Interview Q&A Bank
      • Pipeline and Out-of-Order Questions
      • Caches and Virtual Memory Questions
      • Interconnect Fabric Questions
      • Coherence and Ordering Questions
      • Performance Method Questions
      • Accelerator Questions
      • System Tradeoff Questions
      • Behaviour and Method Questions
Loading lesson

‹Architecture Interview Q&A Bank
  1. Topics
  2. Computer Architecture
  3. Architecture Interview Prep
  4. Architecture Interview Q&A Bank
  5. Caches and Virtual Memory Questions

Computer Architecture · All levels

Caches and Virtual Memory Questions

Cache organization, replacement, prefetching, inclusion and TLB questions with AMAT arithmetic.

On this page

    Miss rate is not the metric

    AMAT combines hit time, miss rate and miss penalty. A lower miss rate can still lose IPC when it buys longer hit latency or a heavier penalty.

    Memory-level parallelism further discounts raw miss counts. Overlapping misses share one penalty, so exposed latency decides throughput, not total misses.

    Check yourself Why is miss rate alone insufficient for hierarchy decisions?

    Performance follows miss penalty, overlap and any hit-latency shift, not the rate. A larger but slower cache can cut the rate while raising AMAT and hurting IPC.

    Check yourself How do you separate a coherence storm from ordinary contention?

    Look for surges in invalidations, replays and retries plus protocol-state anomalies. Plain contention shows queue pressure without that protocol signature.

    Diagram
    AMAT from stated parameters
    formula:  AMAT = hit_time + miss_rate x miss_penalty
    example:  hit_time = 2 cycles, miss_rate = 4 percent, miss_penalty = 180 cycles
    result:   2 + 0.04 x 180 = 2 + 7.2 = 9.2 cycles per access

    The model below checks AMAT arithmetic against hand calculation. It is an arithmetic check, not a hardware model.

    amat_model.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    module amat_model (
      input  logic [15:0] hit_cycles,
      input  logic [15:0] miss_per100,
      input  logic [15:0] miss_penalty,
      output logic [31:0] amat_x100
    );
      always_comb amat_x100 = hit_cycles * 100 + miss_per100 * miss_penalty;
    endmodule
    
    module tb_amat;
      logic [15:0] hit_cycles;
      logic [15:0] miss_per100;
      logic [15:0] miss_penalty;
      logic [31:0] amat_x100;
      amat_model dut (.*);
      int bad = 0;
      initial begin
        hit_cycles = 2; miss_per100 = 4; miss_penalty = 180; #1;
        if (amat_x100 != 920) bad++;
        hit_cycles = 3; miss_per100 = 2; miss_penalty = 120; #1;
        if (amat_x100 != 540) bad++;
        if (bad == 0) $display("PASS: amat gives 9.20 and 5.40 cycles for the two hand cases");
        else $display("FAIL: %0d checks wrong", bad);
        $finish;
      end
    endmodule

    Organization and replacement

    Associativity trades conflict misses against hit latency, power and tail latency. Stop adding ways when marginal MPKI gain turns negative against those costs.

    Prefetch pollution and demand misses need separate buckets. Pollution calls for admission and timeliness tuning, while demand misses call for structure or mapping changes.

    Check yourself What shows an associativity increase is not worth it?

    Small MPKI movement together with measurable hit-latency, power or tail-latency regression on target workloads. The structure then costs more than it saves.

    Check yourself How do you detect replacement thrashing quickly?

    Set-level pressure heatmaps plus short line-lifetime spikes aligned with MPKI bursts. Aggregate misses alone cannot localize the hot sets.

    Check yourself When does a prefetcher hurt?

    On streaming or irregular access, useless prefetches evict useful lines and waste bandwidth. Measure MPKI and bandwidth with prefetch on and off before judging.

    Check yourself What does reuse-distance analysis add beyond MPKI?

    It shows whether evicted lines had near-term reuse, which guides insertion and victim policy. MPKI alone cannot distinguish capacity from policy failures.

    Observation

    Likely cause

    Experiment

    MPKI burst on few sets

    Conflict or thrashing

    Raise associativity or re-map and re-measure

    MPKI up with prefetch on

    Pollution

    Gate admission and compare bandwidth

    Flat misses, higher latency

    Hit-time or penalty shift

    Recompute AMAT per level

    Capacity, levels and the TLB

    Add a level when MPKI times penalty times frequency justifies area, power and the extra hit latency. More levels are never free.

    Inclusion simplifies coherence through back-invalidation but evicts outer lines needlessly. The choice is workload dependent, not doctrinal.

    Check yourself When is another cache level justified?

    When the stall product, MPKI times miss penalty, converted to cycles per instruction exceeds the added hit latency plus area and power budget. Prototype with the penalty math first.

    Check yourself What is the inclusion policy debate?

    Inclusive hierarchies simplify coherence but cause eviction traffic in outer levels. Exclusive or non-inclusive designs save capacity at the cost of harder coherence bookkeeping.

    Check yourself How does a TLB miss hurt a workload?

    Each miss triggers a page walk of tens to hundreds of cycles and stalls the pipeline. Sparse pointer-chasing workloads can spend more time walking than accessing data.

    Diagram
    Stall cost of an L2 miss stream
    formula:  stall_CPI = MPKI x miss_penalty / 1000
    example:  MPKI = 8, miss_penalty = 120 cycles, fully exposed without overlap
    result:   8 x 120 / 1000 = 960 / 1000 = 0.96 cycles per instruction

    Common mistakes

    Common pitfall

    Approving larger caches from miss rate alone repeats the oldest hierarchy error. Recompute AMAT with the new hit time and penalty, and confirm IPC on target workloads.

    Interview

    Likely probes: AMAT arithmetic, pollution versus demand misses, and inclusion tradeoffs.

    • AMAT equals hit time plus miss rate times miss penalty, with overlap stated.

    • Pollution needs admission tuning; demand misses need structure or mapping.

    • Inclusion simplifies coherence and wastes capacity; state the workload reason.

    Check yourself Workload IPC fell 15 percent after a cache change. What are the first three checks?

    MPKI by level, bandwidth utilization per hop, and the stall breakdown into frontend, backend and memory. Those three separate structure, throughput and overlap effects.

    Related topics

    • Caches

    • Memory bandwidth and latency

    • Virtual memory and TLB

    Previous

    80 / 86

    Next: Interconnect Fabric Questions

    Up next

    Up nextInterconnect Fabric Questions

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Coherence and Ordering Questions
    • Performance Method Questions
    • Accelerator Questions