Coherence keeps one value view per address over time. Ordering decides when operations from different addresses become visible relative to each other.
The MESI safety invariant is single writer or multiple readers. At most one cache holds a line with write permission while every reader stays consistent with that ownership.
State | Meaning | Read | Write |
|---|---|---|---|
I (Invalid) | No valid copy | Miss, fetch from owner or memory | Miss, fetch ownership first |
E (Exclusive) | Sole clean copy | Hit, stay Exclusive | Upgrade silently to Modified |
S (Shared) | One of several clean copies | Hit | Invalidate sharers, move to Modified |
M (Modified) | Sole dirty copy | Hit | Hit, already owner |
Coherence gives one value view per address over time. Ordering defines when operations to different addresses become visible relative to each other, which fences and models control.
Single writer or multiple readers: at most one owner with write permission for a line, with readers consistent with that ownership. State names without ownership semantics prove nothing.
MOESI adds an Owned state holding a shared dirty line, which serves other caches without writing back to memory. It cuts off-chip traffic at the cost of harder ownership tracking and verification.
Sequential consistency forbids observable reordering. TSO permits store-load reordering, while ARM and RISC-V RVWMO permit wider reorderings that fences restore.
Litmus tests turn model rules into executable outcomes. Each test names the forbidden result, so hardware teams check implementation against the model directly.
Coherence alone never promised sequential consistency. Without the fences the model requires, weaker cores expose reorderings that the algorithm assumed away.
They convert abstract ordering rules into concrete forbidden outcomes on small programs. A forbidden outcome in silicon is a model violation, not a performance anecdote.
Backpressure changes completion and visibility timing, exposing ordering corners that idle fabrics never show. Light-load barrier tests miss them by construction.
When correctness needs global visibility ordering that acquire and release primitives do not guarantee. Cycle savings never justify an ordering hole.
ACE extends AXI signalling with snoop channels for coherent masters. CHI is a separate decoupled protocol with its own request, response and data channels, not a newer ACE revision.
A practical migration risk is attribute mapping: ordering attributes and completion semantics that behave differently under credit pressure. Throughput parity alone cannot prove the mapping.
ACE adds snoop coherence to AXI-style channels. CHI replaces the channel structure with decoupled request, response and data transactions. Know which one the SoC IP speaks, because their completion and ordering rules differ.
Cut false sharing through layout and padding, match snoop versus directory to the sharing pattern, revisit line size, and fix data placement. A faster fabric alone moves the same invalidations sooner.
Repro rate falls but invariant monitors still log near-miss patterns. Fewer crashes without clean invariants is suppression, not a fix.
Coherent-fabric traffic mix from stated counters
formula: share_pct = class_bytes / total_bytes x 100
example: 520 MB demand + 180 MB writebacks + 170 MB snoops + 130 MB prefetches = 1000 MB
result: 52 + 18 + 17 + 13 = 100 percent (demand 52, writeback 18, snoop 17, prefetch 13)Who owned, invalidated and acknowledged each line event in order. That causality exposes the stale read that aggregate counters only hint at.