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Name the workload and the target

Each workload class stresses one structure. Streaming stresses bandwidth, pointer-chasing stresses the cache and TLB, sharing stresses coherence.

State the target next: IPC or latency, plus power and area budgets. Assume a 3 GHz core with CPI_base 1.0 unless stated otherwise.

Workload class	Stresses	First metric
Branch-heavy control	Fetch and predictor	Mispredicts per kilo-instructions
Pointer-chasing	D-cache, TLB, LLC, DRAM	MPKI by level plus TLB MPKI
Streaming	Prefetcher, bandwidth, NoC	Bytes per cycle vs roof
Sharing across cores	Coherence and line size	Invalidations per kilo-instructions
Accelerator offload	SRAM, DMA, launch path	Active fraction of end-to-end time

Draw the hierarchy and the coherence point

Draw L1I, L1D, L2, L3 and main memory as one path. Mark the coherence point where all observers agree, usually the L3 or the interconnect directory.

Label every arrow with what it carries: requests, responses, invalidations or writebacks. Deadlock and storm analysis both start from this sketch.

Size with MPKI times penalty

Each miss class adds MPKI times penalty over 1000 to CPI. The sum of the classes plus CPI_base is the predicted CPI.

AMAT checks the hierarchy itself: hit time plus miss rate times miss penalty. Both formulas need stated example parameters, never vendor figures.

Diagram

CPI stall add = MPKI x penalty / 1000
  = 8 x 120 cycles / 1000 = 0.96 CPI added
CPI = 1.0 + 0.96 = 1.96, IPC = 1 / 1.96 = 0.51

AMAT = hit + miss_rate x (L2hit + L2miss_rate x DRAMpenalty)
  = 4 + 0.05 x (12 + 0.30 x 200)
  = 4 + 0.05 x 72 = 4 + 3.6 = 7.6 cycles

Check yourself L2 MPKI doubles from 8 to 16 at 120 cycles penalty with CPI_base 1.0. What happens to IPC?

CPI moves from 1.96 to 2.92, so IPC falls from 0.51 to 0.34. The added term is 8 x 120 / 1000 = 0.96 CPI.

Validate with PMU events

Name the counters that would confirm or refute the story. Instructions, cycles, misses per level and stall classes are the minimum set.

One experiment per hypothesis, cheapest first. A counter reading beats a bigger cache as an answer.

Claim	Cheapest PMU check
L2 capacity problem	MPKI by level before and after a footprint change
Conflict misses	MPKI vs set-index histogram or way-miss distribution
TLB reach problem	TLB MPKI plus page-walk cycles
NoC backpressure	Queue occupancies plus per-class injection rates
False sharing	Invalidations per kilo-instructions plus line-bounce sampling

Check yourself The interviewer interrupts the sizing to ask how to check it in silicon. What is the answer?

Name the PMU events: misses per level, stall classes and the one counter that separates the top two hypotheses. Then state the cheapest experiment first.

Related topics

Up nextScenario: Cache MPKI Storm

Practice this lesson Report an error

Name the workload and the target

Each workload class stresses one structure. Streaming stresses bandwidth, pointer-chasing stresses the cache and TLB, sharing stresses coherence.

State the target next: IPC or latency, plus power and area budgets. Assume a 3 GHz core with CPI_base 1.0 unless stated otherwise.

Workload class	Stresses	First metric
Branch-heavy control	Fetch and predictor	Mispredicts per kilo-instructions
Pointer-chasing	D-cache, TLB, LLC, DRAM	MPKI by level plus TLB MPKI
Streaming	Prefetcher, bandwidth, NoC	Bytes per cycle vs roof
Sharing across cores	Coherence and line size	Invalidations per kilo-instructions
Accelerator offload	SRAM, DMA, launch path	Active fraction of end-to-end time

Size with MPKI times penalty

Each miss class adds MPKI times penalty over 1000 to CPI. The sum of the classes plus CPI_base is the predicted CPI.

AMAT checks the hierarchy itself: hit time plus miss rate times miss penalty. Both formulas need stated example parameters, never vendor figures.

Diagram

CPI stall add = MPKI x penalty / 1000
  = 8 x 120 cycles / 1000 = 0.96 CPI added
CPI = 1.0 + 0.96 = 1.96, IPC = 1 / 1.96 = 0.51

AMAT = hit + miss_rate x (L2hit + L2miss_rate x DRAMpenalty)
  = 4 + 0.05 x (12 + 0.30 x 200)
  = 4 + 0.05 x 72 = 4 + 3.6 = 7.6 cycles

Check yourself L2 MPKI doubles from 8 to 16 at 120 cycles penalty with CPI_base 1.0. What happens to IPC?

CPI moves from 1.96 to 2.92, so IPC falls from 0.51 to 0.34. The added term is 8 x 120 / 1000 = 0.96 CPI.

Validate with PMU events

Name the counters that would confirm or refute the story. Instructions, cycles, misses per level and stall classes are the minimum set.

One experiment per hypothesis, cheapest first. A counter reading beats a bigger cache as an answer.

Claim	Cheapest PMU check
L2 capacity problem	MPKI by level before and after a footprint change
Conflict misses	MPKI vs set-index histogram or way-miss distribution
TLB reach problem	TLB MPKI plus page-walk cycles
NoC backpressure	Queue occupancies plus per-class injection rates
False sharing	Invalidations per kilo-instructions plus line-bounce sampling

Check yourself The interviewer interrupts the sizing to ask how to check it in silicon. What is the answer?

Name the PMU events: misses per level, stall classes and the one counter that separates the top two hypotheses. Then state the cheapest experiment first.