Models: SC, TSO, ARMv8, RVWMO · arch

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Coherence is not consistency

Coherence gives a total order of accesses to one location. Every core agrees which store to that address came last.

Consistency constrains visibility across locations. It decides which orders of accesses to different addresses a core may observe.

Concept	Governs	Example
Coherence	One location at a time	Two stores to x reach every core in the same order.
Consistency	Many locations together	Whether a new flag can be seen before new data.

Four models side by side

Pairs read in program order. StLd asks whether a store followed by a load to a different address can appear reordered.

Pair	SC	x86-TSO	ARMv8	RVWMO
StLd	ordered	can reorder	can reorder	can reorder
LdLd	ordered	ordered	can reorder	can reorder
StSt	ordered	ordered	can reorder	can reorder
LdSt	ordered	ordered	can reorder	can reorder

Sequential consistency behaves like some interleaving of program orders. Nothing observable reorders.

x86-TSO adds one FIFO store buffer with forwarding, so only StLd reorders. ARMv8 and RVWMO let any pair reorder, except same-address order and true dependencies.

Pattern	Weak outcome	SC	x86-TSO	ARMv8 / RVWMO
SB	r1 = 0, r2 = 0	never	possible	possible
MP	r1 = 1, r2 = 0	never	never	possible
LB	r1 = 1, r2 = 1	never	never	possible
WRC	reader sees y = 1 yet x = 0	never	never	never
IRIW	two readers disagree on store order	never	never	never

Cumulativity decides WRC and IRIW

A model is multi-copy atomic when a store becomes visible to all cores at once. All four models here have that property, so WRC and IRIW stay forbidden under each.

Those two patterns separated historic non-atomic designs such as old Power and ARMv7. They remain the test for cumulativity when a new implementation claims MCA behavior.

Check yourself x86 code shows SB with r1 = 0, r2 = 0. Which pair reordered, and which fence removes it?

StLd reordered through the store buffer on both cores. An MFENCE between each store and its later load removes it.

Check yourself MP flag arrival with stale data appears on ARMv8. Which pairs explain it, and what removes it?

StSt on the writer side or LdLd on the reader side. A release store with an acquire load, or a full barrier on each side, removes it.

Related topics

Cache coherence for the architect

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Coherence is not consistency

Coherence gives a total order of accesses to one location. Every core agrees which store to that address came last.

Consistency constrains visibility across locations. It decides which orders of accesses to different addresses a core may observe.

Concept	Governs	Example
Coherence	One location at a time	Two stores to x reach every core in the same order.
Consistency	Many locations together	Whether a new flag can be seen before new data.

Four models side by side

Pairs read in program order. StLd asks whether a store followed by a load to a different address can appear reordered.

Pair	SC	x86-TSO	ARMv8	RVWMO
StLd	ordered	can reorder	can reorder	can reorder
LdLd	ordered	ordered	can reorder	can reorder
StSt	ordered	ordered	can reorder	can reorder
LdSt	ordered	ordered	can reorder	can reorder

Sequential consistency behaves like some interleaving of program orders. Nothing observable reorders.

x86-TSO adds one FIFO store buffer with forwarding, so only StLd reorders. ARMv8 and RVWMO let any pair reorder, except same-address order and true dependencies.

Pattern	Weak outcome	SC	x86-TSO	ARMv8 / RVWMO
SB	r1 = 0, r2 = 0	never	possible	possible
MP	r1 = 1, r2 = 0	never	never	possible
LB	r1 = 1, r2 = 1	never	never	possible
WRC	reader sees y = 1 yet x = 0	never	never	never
IRIW	two readers disagree on store order	never	never	never

Cumulativity decides WRC and IRIW

A model is multi-copy atomic when a store becomes visible to all cores at once. All four models here have that property, so WRC and IRIW stay forbidden under each.

Those two patterns separated historic non-atomic designs such as old Power and ARMv7. They remain the test for cumulativity when a new implementation claims MCA behavior.

Check yourself x86 code shows SB with r1 = 0, r2 = 0. Which pair reordered, and which fence removes it?

StLd reordered through the store buffer on both cores. An MFENCE between each store and its later load removes it.

Check yourself MP flag arrival with stale data appears on ARMv8. Which pairs explain it, and what removes it?

StSt on the writer side or LdLd on the reader side. A release store with an acquire load, or a full barrier on each side, removes it.