Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
    • PPA at System Level
    • Power and Energy for the Architect
      • Dynamic Switching Power
      • Static and Leakage Power
      • DVFS and the Energy-Delay Tradeoff
      • Energy per Operation and the Memory Gap
  • Architecture Interview Prep14
Loading lesson

‹Power and Energy for the Architect
  1. Topics
  2. Computer Architecture
  3. SoC Architecture Tradeoffs
  4. Power and Energy for the Architect
  5. DVFS and the Energy-Delay Tradeoff

Computer Architecture · All levels

DVFS and the Energy-Delay Tradeoff

Voltage-frequency scaling, energy-delay product and race-to-halt.

On this page

    What DVFS changes

    DVFS lowers voltage and frequency together for light phases. Power falls roughly with V squared times f, while delay grows roughly with 1 over f.

    Energy is power times delay. DVFS can cut energy while stretching delay, which is the tradeoff this lesson quantifies.

    Worked example

    Take the lesson-1 block: 0.288 W switching at 0.8 V and 3 GHz, running a task in 1 s. Scale to 0.7 V and 2 GHz.

    Diagram
    Power ratio = (V_new^2 x f_new) / (V_old^2 x f_old)
      = (0.49 x 2e9) / (0.64 x 3e9)
      = 0.98 / 1.92
      = 0.5104
    P_new = 0.288 W x 0.5104 = 0.147 W
    Delay_new = 1 s x (3 / 2) = 1.5 s
    E_new = 0.147 W x 1.5 s = 0.2205 J (was 0.288 J)

    Energy fell about 23 percent while delay rose 50 percent. The energy-delay product tells whether that trade was worth it.

    Diagram
    EDP_old = 0.288 J x 1 s = 0.288 J-s
    EDP_new = 0.2205 J x 1.5 s = 0.331 J-s
    EDP rose, so this point buys energy at a steep delay cost.

    When slowing down loses

    Static power does not scale with frequency. Stretching delay burns leakage longer, and past some point total energy rises.

    Add the lesson-2 leakage of 0.4 W to both points above. The slow point then uses more total energy, which favors racing to halt.

    Diagram
    E_total_old = (0.288 W + 0.4 W) x 1 s = 0.688 J
    E_total_new = (0.147 W + 0.4 W) x 1.5 s = 0.547 W x 1.5 s = 0.8205 J
    The slow point costs more energy once leakage dominates.

    Common mistakes

    Common pitfall

    DVFS is not free energy. Below the point where leakage energy exceeds the switching saving, slower means more total energy, not less.

    Interview

    Likely probe: when to race to halt. Answer: when static power dominates, finishing fast and sleeping beats running slow, because slow stretches the leakage bill.

    Check yourself Two operating points have equal energy but one is slower. Which has the better energy-delay product?

    The faster one. Equal energy times smaller delay gives a smaller product.

    Check yourself Leakage is negligible. Does halving frequency at fixed voltage change total energy?

    No. Power halves but delay doubles, so energy is unchanged. Only voltage cuts lower the energy.

    Related topics

    • Dynamic Switching Power

    • Energy per Operation and the Memory Gap

    • Roofline and tuning

    Previous

    71 / 86

    Next: Energy per Operation and the Memory Gap

    Up next

    Up nextEnergy per Operation and the Memory Gap

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Dynamic Switching Power