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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
    • PPA at System Level
    • Power and Energy for the Architect
      • Dynamic Switching Power
      • Static and Leakage Power
      • DVFS and the Energy-Delay Tradeoff
      • Energy per Operation and the Memory Gap
  • Architecture Interview Prep14
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‹Power and Energy for the Architect
  1. Topics
  2. Computer Architecture
  3. SoC Architecture Tradeoffs
  4. Power and Energy for the Architect
  5. Static and Leakage Power

Computer Architecture · All levels

Static and Leakage Power

Leakage sources, power gating and retention, with worked numbers.

On this page

    Where leakage comes from

    Leakage flows even when nothing switches. Subthreshold conduction dominates in modern processes, with gate and junction leakage adding smaller shares.

    Subthreshold current grows exponentially as threshold voltage falls. It also rises steeply with temperature, which couples power to thermals.

    Worked example

    Static power is voltage times leak current. Assume V = 0.8 V and I_leak = 0.5 A for one block.

    Diagram
    P_static = V x I_leak
      = 0.8 V x 0.5 A
      = 0.4 W = 400 mW

    Assume a sleep transistor cuts that block to 8 mW in sleep. The saving is 392 mW, about 98 percent of the leakage.

    Diagram
    P_saved = P_static - P_sleep
      = 400 mW - 8 mW
      = 392 mW (392 / 400 = 98 percent)

    Leakage controls

    Technique

    What it does

    Cost

    Multi-Vt cells

    Slow low-leakage cells off critical paths

    Less speedup where used

    Power gating

    Sleep transistor cuts supply to idle blocks

    Wakeup latency and rush current

    Retention registers

    Keep state at low voltage during sleep

    Extra area and control

    Body biasing

    Shift threshold to trade speed for leakage

    Process and design complexity

    Full gating loses state, so blocks needing fast resume use retention. The choice is wakeup latency against sleep leakage.

    Common mistakes

    Common pitfall

    Gating the clock does not gate leakage. Clock gating cuts switching power only; a clock-gated but powered block still leaks.

    Interview

    Likely probe: clock gating versus power gating. Answer: clock gating stops toggles and keeps state, while power gating stops leakage and loses state unless retention is added.

    Check yourself A block is clock-gated 90 percent of the time but stays powered. Which power term remains?

    Static leakage remains at full value. Only the switching term fell.

    Check yourself Why does leakage make hot chips hotter in a loop?

    Leakage rises with temperature, and the extra power raises temperature further. The loop stops only when cooling balances it.

    Related topics

    • Dynamic Switching Power

    • DVFS and the Energy-Delay Tradeoff

    • System-level PPA tradeoffs

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    See also

    • Energy per Operation and the Memory Gap