Double buffering fills one tile while the array consumes the other. Steady state costs the slower side per tile, not the sum.
With 8-cycle fills and 8-cycle computes over 2 tiles, overlap finishes in 26 cycles against 34 sequential, hiding one full fill.
sequential: 8 + 1 + 8 + 8 + 1 + 8 = 34 cycles (fills, 1-cycle starts, computes)
overlapped: 8 + 1 + 8 + 1 + 8 = 26 cycles (first fill, starts, overlapped middle, last compute)
saved = 34 - 26 = 8 cycles = one hidden fillBuffer depth must cover throughput times latency. One beat per cycle against 8 cycles of latency needs at least 8 entries.
Refill time follows from tile bytes over bandwidth. A 16 KiB tile at 32 GB/s needs 16384 / 32e9 = 512 ns, or 512 cycles at 1 GHz.
Term | Value |
|---|---|
Tile bytes | 16384 B |
Bandwidth | 32 GB/s |
Refill time | 512 ns |
Refill cycles at 1 GHz | 512 |
The model below is a two-buffer tile store with a DMA fill port and a summing compute port. The testbench overlaps the second fill with the first compute and checks both sums plus the 26-cycle span.
module dblbuf_sum #(
parameter int N = 8
) (
input logic clk,
input logic rst_n,
input logic fill_wen,
input logic fill_sel,
input logic [7:0] fill_addr,
input logic [7:0] fill_data,
input logic comp_start,
input logic comp_sel,
output logic comp_done,
output logic [15:0] comp_sum
);
logic [7:0] buf_a [N];
logic [7:0] buf_b [N];
int idx;
logic [15:0] acc;
logic busy;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
comp_done <= 1'b0; comp_sum <= 16'd0;
acc <= 16'd0; idx <= 0; busy <= 1'b0;
end else begin
comp_done <= 1'b0;
if (fill_wen) begin
if (!fill_sel) buf_a[fill_addr] <= fill_data;
else buf_b[fill_addr] <= fill_data;
end
if (comp_start) begin
busy <= 1'b1; acc <= 16'd0; idx <= 0;
end else if (busy) begin
if (idx == N - 1) begin
busy <= 1'b0;
comp_done <= 1'b1;
if (!comp_sel) comp_sum <= acc + buf_a[idx];
else comp_sum <= acc + buf_b[idx];
end else begin
if (!comp_sel) acc <= acc + buf_a[idx];
else acc <= acc + buf_b[idx];
idx <= idx + 1;
end
end
end
end
endmodule
8 cycles. Overlap hides the shorter side behind the longer one.
The schedule. Total time returns to the sequential sum, and the array idles during fills.