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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
    • Accelerators for the Architect
      • When an Accelerator Pays Off
      • Dataflow Patterns as Reuse Contracts
      • Systolic Execution and Utilization Cliffs
      • Locality, Scratchpads and Tile Sizing
      • DMA and Double Buffering
      • Integration, Launch Cost and Signoff
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Accelerators for the Architect
  1. Topics
  2. Computer Architecture
  3. Accelerator Architectures
  4. Accelerators for the Architect
  5. Integration, Launch Cost and Signoff

Computer Architecture · All levels

Integration, Launch Cost and Signoff

Coherency choice, launch budgets and tail latency turn a fast block into a shippable product.

On this page

    Coherent or explicit

    A coherent accelerator shares memory with the CPUs through snoop or directory hardware. A non-coherent one moves explicit buffers with clean, invalidate and fence operations.

    Choice

    Hardware pays

    Software pays

    Coherent

    Snoop and directory traffic

    Almost nothing per buffer

    Non-coherent

    Nothing per buffer

    64 cleans plus fence per 4 KiB buffer at 64 B lines

    A 4 KiB buffer holds 4096 / 64 = 64 lines. Non-coherent handoff cleans all 64 before launch.

    Launch budget and queues

    The driver rings a doorbell, the engine fetches descriptors, computes, then raises an interrupt. Each stage has a timeout and a clean restart rule.

    Assume 50 ns fetch plus 400 ns job plus 100 ns interrupt service. Steady state is 550 ns per job, and the timeout is 4 times that plus margin, about 2.5 us.

    Diagram
    per job: 50 ns + 400 ns + 100 ns = 550 ns
    timeout: 4 x 550 ns = 2200 ns + 300 ns margin = 2500 ns = 2.5 us
    queue bound (Little): 32 entries x 20 ns service = 640 ns

    Tail latency and signoff

    Shared fabrics need class guarantees, not averages. Reserve command-response bandwidth, isolate bulk DMA, and read per-class latency distributions.

    Isolation costs real arbitration slots, so the gain is bounded throughput loss, never negligible loss. Signoff stays conditional on owner and expiry.

    Gate

    Pass rule

    Concurrency

    Platform contracts hold under CPU plus accelerator load

    Power transitions

    No command accepted mid-transition, replay storm bounded

    Isolation

    Stream-ID table denies unmapped pages, faults signaled

    Common mistakes

    Common pitfall

    Claiming queue isolation costs nothing repeats the audited overclaim. Reservations move tail latency at a bounded throughput price that the budget must state.

    Interview

    Likely probes: handoff ownership and jitter triage.

    • Name the fence plus clean and invalidate recipe for non-coherent buffers.

    • Triage jitter as arbitration, queues, interrupts, then firmware scheduling.

    • Reject signoff when platform contracts fail, however fast standalone kernels run.

    Check yourself When does non-coherent win?

    When no shared mutable state escapes explicit sync, and the saved snoop traffic beats 64 cleans plus a fence per 4 KiB.

    Check yourself Standalone benchmarks pass but platform latency jitters. What do you audit first?

    Arbitration and queue isolation under concurrency, then interrupt handling and firmware scheduling.

    Related topics

    • Cache coherence for the architect

    • On-chip networks

    • Cache Coherency

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    See also

    • When an Accelerator Pays Off
    • Dataflow Patterns as Reuse Contracts
    • Systolic Execution and Utilization Cliffs