One MAC touches three 1 B operands, so zero reuse costs 3 B per MAC. Reuse divides the traffic of the reused tensor.
Hit rate alone can lie. Bytes per operation at each level is the KPI, paired with energy.
no reuse: 3 operands x 1 B = 3 B per MAC
16x16 output tile: one weight serves 256 outputs -> 1 / 256 B per MAC ≈ 0.0039 B per MAC
AMAT example: 1 + 0.05 x 20 = 1 + 1.0 = 2.0 cyclesA scratchpad holds exactly what the compiler placed. A cache guesses, which helps irregular code and hurts determinism.
Assume 32 KiB of SRAM with double buffering. Each buffer holds 16 KiB, so a tile must fit 16 KiB.
INT8 tile | Bytes | Double-buffered share of 32 KiB |
|---|---|---|
128x128 | 16384 (16 KiB) | 32768 / 32768 = 100%, no headroom |
64x64 | 4096 (4 KiB) | 8192 / 32768 = 25% |
Off-chip movement sets energy and sustained bandwidth. Row-buffer hits, read-write turnaround and concurrency headroom decide what survives.
Compression stays out of this topic. It is listed in legacy plans without traffic math, so no claim is made here.
Report | What it measures |
|---|---|
Bytes per op by level | Traffic per useful MAC at SRAM, NoC and DRAM |
Bank conflict profile | Serialization from strided tile layouts |
DRAM efficiency trend | Row-hit rate and sustained versus peak bandwidth |
The locality assumption. Coherency traffic, burst waste or spill still dominates end to end.
128x128 at 16384 B, exactly one 16 KiB buffer.