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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
    • Memory Bandwidth and Latency
    • Virtual Memory and the TLB
      • Pages and Multi-Level Page Tables
      • TLB Reach and Miss Cost
      • Huge Pages
      • Translation and Cache Indexing
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Virtual Memory and the TLB
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Virtual Memory and the TLB
  5. Translation and Cache Indexing

Computer Architecture · All levels

Translation and Cache Indexing

VIPT caches: why index bits must fit the page offset, with a worked sizing check.

On this page

    Three arrangements

    Caches can be indexed and tagged in either address space. The choice decides whether a lookup waits for translation.

    Arrangement

    Index from

    Tag from

    Cost

    VIVT

    Virtual address

    Virtual address

    No translation wait, but aliases and flushes on context switch.

    VIPT

    Virtual address

    Physical address

    Index starts at once; tag compare waits for the TLB.

    PIPT

    Physical address

    Physical address

    No aliasing, but every access waits for translation.

    The VIPT size rule

    VIPT works like PIPT when the index bits all sit inside the page offset. Those bits are identical in both addresses, so the set is selected before translation finishes.

    That gives the size rule: cache size may not exceed associativity times page size. Larger caches must raise associativity, use larger pages, or go PIPT.

    Diagram
    example: 32 KiB cache, 8-way, 64 B lines, 4 KiB pages
    sets = 32768 / (8 x 64) = 32768 / 512 = 64
    index bits = log2(64) = 6, block offset = log2(64) = 6
    index + offset = 6 + 6 = 12 bits = page offset -> set needs no translation
    rule: size <= associativity x page size = 8 x 4 KiB = 32 KiB -> holds exactly
    counter-example: 64 KiB, 4-way, 64 B lines
    sets = 65536 / (4 x 64) = 65536 / 256 = 256
    index 8 bits + offset 6 bits = 14 bits > 12 -> 2 index bits need translation

    Aliasing

    When index bits cross into the VPN, two virtual addresses can place one physical line in two sets. That synonym problem needs extra handling.

    Systems answer with PIPT caches, higher associativity, page coloring by the OS, or hardware alias checks. Small L1 caches usually just obey the size rule.

    Common mistakes

    Common pitfall

    Growing a VIPT L1 past associativity times page size silently introduces synonyms. Recheck the size rule on every capacity or associativity change.

    Interview

    Likely probes: why VIPT is popular for L1, and where it breaks.

    • Index overlaps translation, so the data array read starts early.

    • The tag still comes from the TLB, so a TLB miss stalls the hit signal.

    • Past the size rule, synonyms appear and PIPT or coloring is needed.

    Check yourself A 32 KiB 8-way cache has 64-byte lines and 4 KiB pages. Why is it alias-free?

    Index plus offset is 12 bits, exactly the page offset. The set index never depends on translation.

    Check yourself The cache in the counter-example grows to 64 KiB at 4-way. How many index bits need translation?

    Two. Index plus offset is 14 bits against a 12-bit page offset, so the top 2 index bits come from the VPN.

    Related topics

    • Pages and multi-level walks

    • Caches

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    See also

    • Pages and Multi-Level Page Tables
    • TLB Reach and Miss Cost