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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
    • Memory Bandwidth and Latency
    • Virtual Memory and the TLB
      • Pages and Multi-Level Page Tables
      • TLB Reach and Miss Cost
      • Huge Pages
      • Translation and Cache Indexing
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Virtual Memory and the TLB
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Virtual Memory and the TLB
  5. Huge Pages

Computer Architecture · All levels

Huge Pages

Huge pages: fewer levels, fewer entries, larger TLB reach, and fragmentation cost.

On this page

    Fewer levels, fewer entries

    A 2 MiB page uses a 21-bit offset, and a 1 GiB page uses a 30-bit offset. The leftover VPN bits need fewer table levels.

    A 2 MiB mapping skips the leaf level, so its walk reads three tables. A 1 GiB mapping skips two levels and reads two tables.

    Page size

    Offset bits

    Walk reads

    PTEs per 1 GiB

    4 KiB

    12

    4

    262144

    2 MiB

    21

    3

    512

    1 GiB

    30

    2

    1

    Reach per entry

    Each huge-page TLB entry maps far more memory. A small set of huge entries can cover a large buffer that thousands of 4 KiB entries could not.

    Diagram
    1 GiB region: 2^30 B
    4 KiB PTEs: 2^30 / 2^12 = 2^18 = 262144
    2 MiB PTEs: 2^30 / 2^21 = 2^9 = 512
    1 GiB PTEs: 2^30 / 2^30 = 1
    TLB reach: 32 entries x 2 MiB = 32 x 2097152 B = 67108864 B = 64 MiB

    Costs of bigness

    Huge pages need large contiguous, aligned physical blocks. After long uptime the allocator may fail to find one, and the mapping falls back to 4 KiB pages.

    A 10 KiB structure in a 2 MiB page wastes nearly the whole page. That internal fragmentation is the price of the extra reach.

    Benefit

    Cost

    Larger reach per TLB entry

    Needs contiguous aligned physical memory.

    Shorter walks and fewer PTEs

    Internal fragmentation for small mappings.

    Fewer TLB misses for big buffers

    Mixed sizes complicate replacement and shootdowns.

    Common mistakes

    Common pitfall

    Mapping everything huge wastes memory and can slow allocation to a crawl. Reserve huge pages for large, long-lived buffers and leave the rest at 4 KiB.

    Interview

    Likely probes: when huge pages win and what breaks.

    • Big sequential buffers win: fewer misses, shorter walks, fewer PTEs.

    • Fragmentation and contiguity are the costs; fallback to 4 KiB must exist.

    • Permissions still apply per huge page; a fault covers the whole range.

    Check yourself How many 2 MiB pages cover 1 GiB, and how many table reads does each walk take?

    512 pages. Three reads, since the leaf level is skipped.

    Check yourself A 32-entry huge-page TLB uses 2 MiB pages. What is its reach?

    64 MiB. Each entry maps 2 MiB, so 32 times 2 MiB is 64 MiB.

    Related topics

    • TLB reach and miss cost

    • Translation and cache indexing

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    See also

    • Pages and Multi-Level Page Tables