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Course contents

  • Architecture Metrics Reference
  • Workload Taxonomy for Architects
  • Architecture Glossary
  • Computer Architecture Cheatsheet
  • Pipeline Fundamentals14
  • Memory Hierarchy15
    • Caches
    • Memory Bandwidth and Latency
    • Virtual Memory and the TLB
      • Pages and Multi-Level Page Tables
      • TLB Reach and Miss Cost
      • Huge Pages
      • Translation and Cache Indexing
  • NoC and Interconnect Architecture6
  • Coherency and Memory Ordering9
  • Performance Analysis9
  • Accelerator Architectures6
  • SoC Architecture Tradeoffs9
  • Architecture Interview Prep14
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‹Virtual Memory and the TLB
  1. Topics
  2. Computer Architecture
  3. Memory Hierarchy
  4. Virtual Memory and the TLB
  5. Pages and Multi-Level Page Tables

Computer Architecture · All levels

Pages and Multi-Level Page Tables

Pages, page-table entries, and four-level walks with a worked address split.

On this page

    Pages and entries

    A 4 KiB page means the low 12 address bits are the offset within the page. The remaining upper bits are the virtual page number (VPN).

    Translation replaces the VPN with a physical page number (PPN) and keeps the offset. One entry (PTE) maps one page and carries permission bits.

    PTE field

    Purpose

    Present

    Set when the page is resident; clear raises a page fault.

    Read/write

    Write permission; a store to a read-only page faults.

    User/supervisor

    Whether user code may access the page.

    Accessed / dirty

    Set by hardware on first access and first store; used by page replacement.

    PPN

    The physical page number the VPN maps to.

    Four levels

    A single flat table for a 48-bit virtual address would need 2^36 entries. No system stores that, so the table is a four-level tree with 9 bits per level.

    Each table holds 512 entries of 8 bytes, exactly one 4 KiB page. The root pointer plus four 9-bit indices locate the PTE.

    VA bits

    Field

    Meaning

    47:39

    Level 4 index

    9 bits into the root table.

    38:30

    Level 3 index

    9 bits into the next table.

    29:21

    Level 2 index

    9 bits into the next table.

    20:12

    Level 1 index

    9 bits into the leaf table.

    11:0

    Page offset

    12 bits copied unchanged to the physical address.

    A worked split

    Take indices L4 = 1, L3 = 2, L2 = 3, L1 = 4 and offset 0x567. The calc block builds the address term by term.

    Diagram
    48-bit VA, 4 KiB pages, 4 levels of 9 bits: 9 + 9 + 9 + 9 + 12 = 48
    VA = L4 * 2^39 + L3 * 2^30 + L2 * 2^21 + L1 * 2^12 + offset
       = 1 * 549755813888 + 2 * 1073741824 + 3 * 2097152 + 4 * 4096 + 1383
       = 549755813888 + 2147483648 + 6291456 + 16384 + 1383
       = 551909606759 = 0x008080604567
    check: VA[47:39] = 1, VA[38:30] = 2, VA[29:21] = 3, VA[20:12] = 4, VA[11:0] = 0x567

    What a walk costs

    A full walk reads four tables, one per level. Each read that misses the caches costs a memory access.

    Diagram
    assume each table read costs 80 ns of DRAM
    full walk = 4 reads x 80 ns = 320 ns
    assume a 3 GHz core, 1 cycle = 0.333 ns
    walk cycles = 320 ns / 0.333 ns = 960 cycles
    with page-walk caches assume 60 cycles per walk (stated example parameter)

    Common mistakes

    Common pitfall

    A missing present bit and a failed permission check both fault, but the fixes differ. The first needs the page brought in; the second is a protection bug in the program or its mappings.

    Interview

    Likely probes: why four levels, and what each walk step reads.

    • Four levels of 9 bits cover 36 VPN bits with tables of one page each.

    • Each step adds one base-plus-index read; the leaf PTE gives the PPN.

    • A full DRAM walk is about 4 memory reads; cached walks cost far less.

    Check yourself A 4 KiB page system uses a 48-bit virtual address. How many bits are VPN, and how do four levels cover them?

    VPN is 36 bits (48 minus 12 offset). Four levels of 9 bits cover exactly 36 bits.

    Check yourself Each PTE is 8 bytes and a table fills one 4 KiB page. How many entries per table, and how many index bits is that?

    4096 / 8 = 512 entries. 512 is 2^9, so 9 index bits.

    Related topics

    • TLB reach and miss cost

    • Caches

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    See also

    • Huge Pages
    • Translation and Cache Indexing