Walk me through what happens after RTL freeze until tapeout — what are the major checkpoints?
CLOSURE CHAIN
1. METRIC — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regressSTAGE INPUTS OUTPUTS / METRICS
─────────────────────────────────────────────────────────────────
Synthesis RTL, SDC, libs Netlist, area, initial WNS
Floorplan Netlist, DEF template Die size, util, macro sites
Placement Floorplan, netlist Legal cells, congestion map
CTS Placed design, SDC Skew/latency, hold fixes
Routing CTS netlist Routed design, DRV, antenna
STA signoff Routed, SDC, SPEF WNS/TNS per corner/mode
Power Grid + activity IR, EM reports
PV GDS/OASIS DRC, LVS, density, fill
Tapeout Signed GDS Mask data, documentationSynthesis optimizes logic before physical awareness — not final signoff timing.
Floorplan mistakes are expensive — utilization and macro channels drive congestion.
CTS inserts hold buffers — hold failures often appear after CTS, not before.
Routing fixes connectivity and layer usage — can degrade timing if congested.
Signoff is multi-corner multi-mode — one passing corner is not done.
Synthesis: unconstrained paths? mapping to intended VT cells?
Floorplan: macro halos respected? power strap pitch adequate?
Placement: congestion hotspots correlated with macro channels?
CTS: skew within spec? clock gating cells placed legally?
Route: DRV clean? antenna rules satisfied?
Signoff: all corners closed? waiver list documented?
Know who owns each stage in your organization — PD vs CAD vs DFT.
Closure is iterative — expect multiple place/CTS/route loops.
Treating synthesis WNS as signoff — missing SI, OCV, propagated clocks.
Skipping floorplan review — macro placement drives 80% of congestion pain.
Single-corner closure — hold fails at opposite corner late in project.
Every PD stage changes the validity of previous reports. Pre-route timing ignores final parasitics; pre-CTS timing ignores real clock insertion; pre-fill extraction misses fill capacitance. Treat each handoff as a new evidence checkpoint.
After CTS, rerun setup and hold; do not trust pre-CTS hold.
After route, re-extract; do not trust placement estimates.
After fill, re-check density, DRC, and critical timing.
Lesson pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.