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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
    • Core Ring Design
    • Strap Pitch and Layer Selection
    • Follow-Pin and Standard-Cell Rails
    • Macro Power Hookup
    • Decap Planning
    • Power Domain Grid Partitioning
    • Early IR Analysis
    • Power Planning Tricky Q&A
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Physical Design
  1. Topics
  2. Physical Design
  3. Power Planning

Physical Design · All levels

Power Planning

Plan and validate block-level power delivery architecture from ring/strap topology through early IR analysis and domain partitioning.

  • 8topics
  • 57lessons

Topics in this section

  1. 1Core Ring Design8 lessons
    • Core Ring Design — Mechanism
    • Core Ring Design — Inputs & Outputs
    • Core Ring Design — Reports & Metrics
    • Core Ring Design — Debug Playbook
    • Core Ring Design — Worked Example
    • Core Ring Design — Pitfalls & Red Flags
    • Core Ring Design — Interview Drills
    • Core Ring Design — Review Checklist
  2. 2Strap Pitch and Layer Selection8 lessons
    • Strap Pitch and Layer Selection — Mechanism
    • Strap Pitch and Layer Selection — Inputs & Outputs
    • Strap Pitch and Layer Selection — Reports & Metrics
    • Strap Pitch and Layer Selection — Debug Playbook
    • Strap Pitch and Layer Selection — Worked Example
    • Strap Pitch and Layer Selection — Pitfalls & Red Flags
    • Strap Pitch and Layer Selection — Interview Drills
    • Strap Pitch and Layer Selection — Review Checklist
  3. 3Follow-Pin and Standard-Cell Rails8 lessons
    • Follow-Pin and Standard-Cell Rails — Mechanism
    • Follow-Pin and Standard-Cell Rails — Inputs & Outputs
    • Follow-Pin and Standard-Cell Rails — Reports & Metrics
    • Follow-Pin and Standard-Cell Rails — Debug Playbook
    • Follow-Pin and Standard-Cell Rails — Worked Example
    • Follow-Pin and Standard-Cell Rails — Pitfalls & Red Flags
    • Follow-Pin and Standard-Cell Rails — Interview Drills
    • Follow-Pin and Standard-Cell Rails — Review Checklist
  4. 4Macro Power Hookup8 lessons
    • Macro Power Hookup — Mechanism
    • Macro Power Hookup — Inputs & Outputs
    • Macro Power Hookup — Reports & Metrics
    • Macro Power Hookup — Debug Playbook
    • Macro Power Hookup — Worked Example
    • Macro Power Hookup — Pitfalls & Red Flags
    • Macro Power Hookup — Interview Drills
    • Macro Power Hookup — Review Checklist
  5. 5Decap Planning8 lessons
    • Decap Planning — Mechanism
    • Decap Planning — Inputs & Outputs
    • Decap Planning — Reports & Metrics
    • Decap Planning — Debug Playbook
    • Decap Planning — Worked Example
    • Decap Planning — Pitfalls & Red Flags
    • Decap Planning — Interview Drills
    • Decap Planning — Review Checklist
  6. 6Power Domain Grid Partitioning8 lessons
    • Power Domain Grid Partitioning — Mechanism
    • Power Domain Grid Partitioning — Inputs & Outputs
    • Power Domain Grid Partitioning — Reports & Metrics
    • Power Domain Grid Partitioning — Debug Playbook
    • Power Domain Grid Partitioning — Worked Example
    • Power Domain Grid Partitioning — Pitfalls & Red Flags
    • Power Domain Grid Partitioning — Interview Drills
    • Power Domain Grid Partitioning — Review Checklist
  7. 7Early IR Analysis8 lessons
    • Early IR Analysis — Mechanism
    • Early IR Analysis — Inputs & Outputs
    • Early IR Analysis — Reports & Metrics
    • Early IR Analysis — Debug Playbook
    • Early IR Analysis — Worked Example
    • Early IR Analysis — Pitfalls & Red Flags
    • Early IR Analysis — Interview Drills
    • Early IR Analysis — Review Checklist
  8. 8Power Planning Tricky Q&A1 lesson
On this page

    Section goal

    Build a power grid that is IR/EM robust while preserving routability and ECO flexibility.

    Mechanism to narrate

    • Power planning is a closure enabler, not a post-route patch.

    • Grid decisions should be tied to measurable current demand and droop budgets.

    • Domain boundaries and macro hooks must be explicit before placement ramps.

    Senior course bar for this section

    • Every topic should end with a signoff decision, not only concept recall.

    • Every fix should state expected metric movement and likely regression surface.

    • Every open assumption should have an owner, tag, and review date.

    • Every recurring issue should become a methodology guardrail or checklist item.

    1. core-ring-design/ — Core Ring Design

    2. strap-pitch-and-layer-selection/ — Strap Pitch and Layer Selection

    3. follow-pin-and-stdcell-rails/ — Follow-Pin and Standard-Cell Rails

    4. macro-power-hookup/ — Macro Power Hookup

    5. decap-planning/ — Decap Planning

    6. power-domain-grid-partitioning/ — Power Domain Grid Partitioning

    7. early-ir-analysis/ — Early IR Analysis

    Related topics

    • Floorplanning Expanded

    • Placement

    • Power Signoff

    Key takeaways

    • Tune ring, straps, rails, and decap as one system.

    • Run early IR often enough to catch topology mistakes before route congestion hardens.

    Detailed section notes

    Interview performance is structured closure thinking under time pressure.

    Reports and artifacts to inspect

    • one-slide metric dashboard for the scenario

    • hypothesis list sorted by likelihood and cost

    • one report/map per experiment

    • regression list after the proposed fix

    Mini case study

    A strong answer to any scenario starts with the failing metric and signoff context. A weak answer starts with a tool command or random optimization knob.

    Debug branches

    • If you are stuck, restate the metric and ask for corner/mode/stage.

    • If multiple failures exist, separate hard gates from tracked risks.

    • If pressured to waive, describe approval path and silicon risk.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Hub pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    PreviousNext: Core Ring Design

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    See also

    • How to Use This Course
    • PD Flow Overview — RTL to GDSII
    • Data & Libraries — What PD Receives