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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Physical Design
  1. Topics
  2. Physical Design
  3. PD Closure Cheat Sheet

Physical Design · All levels

PD Closure Cheat Sheet

One-page reference: closure chain, fix order, signoff gates, report checklist, escalation.

On this page

    Closure chain (say first in any interview)

    Diagram
    METRIC → HYPOTHESIS → EXPERIMENT → FIX → REGRESSION
    
      METRIC:     WNS/TNS, corner, mode, path pin names
      HYPOTHESIS: ordered causes (no random tweaks)
      EXPERIMENT: one report/map before changing layout
      FIX:        minimal physical/constraint/RTL change
      REGRESSION: corners, modes, DRV, LVS, IR re-run

    Fix order — setup (post-route)

    Diagram
    1. Verify SDC tag + corner + mode + SI on
    2. Path report: net delay vs cell delay
    3. RTL pipeline (if allowed)
    4. Layer up / spread placement / CTS latency
    5. Size / VT swap / buffer / useful skew (hold risk)
    6. ECO metal/cell — document tag

    Fix order — hold (often post-CTS)

    Diagram
    1. Hold corner report (often BC fast)
    2. Short data paths — insert delay/buffer
    3. Skew adjust if budget (check setup regression)
    4. Hold-specific opt pass — cluster by clock domain

    Congestion fix order

    Diagram
    1. Map hotspot ↔ macro channel / pin escape
    2. Macro rotate / widen channel / soft blockage
    3. Spread placement density
    4. Layer promotion / routing preference
    5. Drop util 3–5% or die bump

    Signoff hard gates

    • LVS clean (connectivity)

    • DRC clean or approved waivers only

    • STA matrix: setup @ WC + hold @ BC (all modes)

    • IR/EM @ agreed vectors

    • Revision tag matches GDS + SDC + netlist

    Reports to name in interviews

    Diagram
    Timing:  report_timing -max/-min, path slack, clock latency
    Route:   congestion map, DRV summary
    CTS:     skew/latency histogram
    Power:   IR map, EM ratio report
    PV:      DRC count by rule, LVS compare
    Signoff: closure dashboard one slide

    Escalation — when to stop tweaking

    • LVS fail → stop tapeout timeline until clean

    • Wrong revision tag → stop all exports

    • IR > spec with timing margin thin → escalate to architect + power lead

    • Systematic DRC >100 → cluster fix meeting, not hero edits

    Related topics

    • Closure framework

    • Metrics dashboard

    Key takeaways

    • Name corner before fix — every time.

    • Congestion before timing opt on unroutable nets.

    How to use this sheet in interviews

    Do not recite this sheet linearly. Use it as a mental index. When the interviewer gives a failure, jump to the corresponding fix order and narrate the evidence you need before making a change.

    Self-check

    • Timing failure: corner, mode, WNS/TNS, path report.

    • Physical failure: DRC/LVS rule, cluster, owner, waiver policy.

    • Power failure: IR/EM metric, vector, hotspot, grid fix.

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    See also

    • How to Use This Course
    • PD Flow Overview — RTL to GDSII
    • Data & Libraries — What PD Receives