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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
    • DRC, LVS, and ERC Convergence Flow
    • Metal Density Fill Strategy
    • Antenna and LVS Cross-Debug
    • PV Waiver Policy and Auditability
    • Hierarchical LVS Debug Playbook
    • Fill and Timing Correlation
    • Systematic DRC Pattern Debug
    • Tapeout PV Signoff Gate
    • Physical Verification Tricky Q&A
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Physical Design
  1. Topics
  2. Physical Design
  3. Physical Verification

Physical Design · All levels

Physical Verification

Expanded physical verification registry covering DRC/LVS/ERC closure, fill effects, waiver discipline, and tapeout readiness.

  • 9topics
  • 65lessons

Topics in this section

  1. 1DRC, LVS, and ERC Convergence Flow8 lessons
    • DRC, LVS, and ERC Convergence Flow — Mechanism
    • DRC, LVS, and ERC Convergence Flow — Inputs & Outputs
    • DRC, LVS, and ERC Convergence Flow — Reports & Metrics
    • DRC, LVS, and ERC Convergence Flow — Debug Playbook
    • DRC, LVS, and ERC Convergence Flow — Worked Example
    • DRC, LVS, and ERC Convergence Flow — Pitfalls & Red Flags
    • DRC, LVS, and ERC Convergence Flow — Interview Drills
    • DRC, LVS, and ERC Convergence Flow — Review Checklist
  2. 2Metal Density Fill Strategy8 lessons
    • Metal Density Fill Strategy — Mechanism
    • Metal Density Fill Strategy — Inputs & Outputs
    • Metal Density Fill Strategy — Reports & Metrics
    • Metal Density Fill Strategy — Debug Playbook
    • Metal Density Fill Strategy — Worked Example
    • Metal Density Fill Strategy — Pitfalls & Red Flags
    • Metal Density Fill Strategy — Interview Drills
    • Metal Density Fill Strategy — Review Checklist
  3. 3Antenna and LVS Cross-Debug8 lessons
    • Antenna and LVS Cross-Debug — Mechanism
    • Antenna and LVS Cross-Debug — Inputs & Outputs
    • Antenna and LVS Cross-Debug — Reports & Metrics
    • Antenna and LVS Cross-Debug — Debug Playbook
    • Antenna and LVS Cross-Debug — Worked Example
    • Antenna and LVS Cross-Debug — Pitfalls & Red Flags
    • Antenna and LVS Cross-Debug — Interview Drills
    • Antenna and LVS Cross-Debug — Review Checklist
  4. 4PV Waiver Policy and Auditability8 lessons
    • PV Waiver Policy and Auditability — Mechanism
    • PV Waiver Policy and Auditability — Inputs & Outputs
    • PV Waiver Policy and Auditability — Reports & Metrics
    • PV Waiver Policy and Auditability — Debug Playbook
    • PV Waiver Policy and Auditability — Worked Example
    • PV Waiver Policy and Auditability — Pitfalls & Red Flags
    • PV Waiver Policy and Auditability — Interview Drills
    • PV Waiver Policy and Auditability — Review Checklist
  5. 5Hierarchical LVS Debug Playbook8 lessons
    • Hierarchical LVS Debug Playbook — Mechanism
    • Hierarchical LVS Debug Playbook — Inputs & Outputs
    • Hierarchical LVS Debug Playbook — Reports & Metrics
    • Hierarchical LVS Debug Playbook — Debug Playbook
    • Hierarchical LVS Debug Playbook — Worked Example
    • Hierarchical LVS Debug Playbook — Pitfalls & Red Flags
    • Hierarchical LVS Debug Playbook — Interview Drills
    • Hierarchical LVS Debug Playbook — Review Checklist
  6. 6Fill and Timing Correlation8 lessons
    • Fill and Timing Correlation — Mechanism
    • Fill and Timing Correlation — Inputs & Outputs
    • Fill and Timing Correlation — Reports & Metrics
    • Fill and Timing Correlation — Debug Playbook
    • Fill and Timing Correlation — Worked Example
    • Fill and Timing Correlation — Pitfalls & Red Flags
    • Fill and Timing Correlation — Interview Drills
    • Fill and Timing Correlation — Review Checklist
  7. 7Systematic DRC Pattern Debug8 lessons
    • Systematic DRC Pattern Debug — Mechanism
    • Systematic DRC Pattern Debug — Inputs & Outputs
    • Systematic DRC Pattern Debug — Reports & Metrics
    • Systematic DRC Pattern Debug — Debug Playbook
    • Systematic DRC Pattern Debug — Worked Example
    • Systematic DRC Pattern Debug — Pitfalls & Red Flags
    • Systematic DRC Pattern Debug — Interview Drills
    • Systematic DRC Pattern Debug — Review Checklist
  8. 8Tapeout PV Signoff Gate8 lessons
    • Tapeout PV Signoff Gate — Mechanism
    • Tapeout PV Signoff Gate — Inputs & Outputs
    • Tapeout PV Signoff Gate — Reports & Metrics
    • Tapeout PV Signoff Gate — Debug Playbook
    • Tapeout PV Signoff Gate — Worked Example
    • Tapeout PV Signoff Gate — Pitfalls & Red Flags
    • Tapeout PV Signoff Gate — Interview Drills
    • Tapeout PV Signoff Gate — Review Checklist
  9. 9Physical Verification Tricky Q&A1 lesson
On this page

    Section goal

    Drive PV closure with evidence-backed debug, not brute-force reruns.

    Mechanism to narrate

    • Classify violations by mechanism before assigning fixes.

    • Track report version, deck version, and database tag on every review.

    • Treat waivers as managed risk with owner and expiry, not a schedule shortcut.

    Senior course bar for this section

    • Every topic should end with a signoff decision, not only concept recall.

    • Every fix should state expected metric movement and likely regression surface.

    • Every open assumption should have an owner, tag, and review date.

    • Every recurring issue should become a methodology guardrail or checklist item.

    1. drc-lvs-erc-flow/ — DRC, LVS, and ERC Convergence Flow

    2. metal-density-fill/ — Metal Density Fill Strategy

    3. antenna-lvs-debug/ — Antenna and LVS Cross-Debug

    4. pv-waiver-policy/ — PV Waiver Policy and Auditability

    5. lvs-hierarchical-debug/ — Hierarchical LVS Debug Playbook

    6. fill-and-timing-impact/ — Fill and Timing Correlation

    7. drc-pattern-debug/ — Systematic DRC Pattern Debug

    8. tapeout-pv-signoff/ — Tapeout PV Signoff Gate

    Related topics

    • Routing prerequisite topics

    • Signoff and tapeout handoff

    Key takeaways

    • PV closure means DRC/LVS/ERC health plus reproducible evidence trail.

    Detailed section notes

    Physical verification is the manufacturing and connectivity gate.

    Reports and artifacts to inspect

    • DRC report grouped by rule and bounding-box cluster

    • LVS compare: opens, shorts, device mismatches, parameter mismatches

    • ERC checks: floating gates, power/ground, soft connects

    • density/fill report by layer and window

    Mini case study

    DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.

    Debug branches

    • If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.

    • If DRC violations cluster, fix the systematic rule before editing isolated shapes.

    • If fill changes route capacitance, re-extract and re-run critical timing checks.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Hub pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    PreviousNext: DRC, LVS, and ERC Convergence Flow

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    See also

    • How to Use This Course
    • PD Flow Overview — RTL to GDSII
    • Data & Libraries — What PD Receives