Antenna and LVS Cross-Debug — Reports & Metrics

On-call / interview prompt

Which report lines prove Antenna and LVS Cross-Debug is healthy vs failing?

CLOSURE CHAIN

1. METRIC     — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX        — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regress

Reports to inspect

• Antenna ratio violation list with victim net lengths

• LVS compare report for added/removed devices

• Connectivity cross-probe log for changed nets

REPORT SNIPPET — Antenna and LVS Cross-Debug
  metric_A: <value>  (spec: <limit>)
  metric_B: <value>  (spec: <limit>)
  worst_region: <name>
  recommended_action: <one line>

Smoke check (5 minutes)

• Can you name the single worst line in the report?

• Can you tie that line to a physical region on the floorplan or layout?

How to read this like a signoff lead

The report is not a pass/fail artifact; it is a prioritization tool. Read Physical Verification closure dashboard by severity, locality, trend, and fix cost before touching the design.

Report triage order

1. Confirm database tag, corner, mode, extraction state, and analysis switches.

2. Separate hard gates from tracked risks and cosmetic noise.

3. Cluster failures by physical region, hierarchy, clock domain, power domain, or rule class.

4. Compare against previous tag to identify new regressions, not just absolute failures.

5. Translate the worst line into an owner, experiment, and rollback plan.

SENIOR REPORT READOUT
  worst_line: <copy exact report line>
  cluster: <region/domain/rule/path-group>
  delta_from_previous: <new/worse/better/same>
  first_experiment: <cheap evidence-gathering action>
  decision: <fix now / assign owner / waive with approval / stop release>

Deep dive: how this shows up in real closure

Physical verification is the manufacturing and connectivity gate.

Reports and artifacts to inspect

• DRC report grouped by rule and bounding-box cluster

• LVS compare: opens, shorts, device mismatches, parameter mismatches

• ERC checks: floating gates, power/ground, soft connects

• density/fill report by layer and window

Mini case study

DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.

Debug branches

• If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.

• If DRC violations cluster, fix the systematic rule before editing isolated shapes.

• If fill changes route capacitance, re-extract and re-run critical timing checks.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

• You are expected to predict what your fix can break before running it.

• You should recognize when the issue is methodology, not one block's implementation.

• You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

• Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

• Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

• Chooses experiments by information gain and reversibility, not by habit.

• States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

• Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

• What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

• Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

• What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

• Always connect the concept back to a measurable signoff artifact.

• A fix is not complete until you can name the regression checks.

Common pitfalls

• Optimizing by habit instead of reading the current report.

• Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.