Antenna diode insertion fixed antenna ratios but introduced LVS device mismatch. What changed and how do you prove it?
CLOSURE CHAIN
1. METRIC — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regressUse a shared debug loop for antenna repairs and LVS mismatches because metal edits often couple both outcomes.
Section: Physical Verification
Primary artifact: see Reports subpage
Downstream dependency: next PD stage
Own Antenna and LVS Cross-Debug as a release decision, not a page of notes. A senior PD engineer names the metric, the physical mechanism, the cross-team dependency, and the smallest evidence-producing experiment.
STAFF REVIEW MEMO — Physical Verification / Antenna and LVS Cross-Debug
1. Current state
- Failing / watched metric: Physical Verification closure dashboard
- Database tag, corner/mode, tool version: <fill before review>
- Physical scope: block, hierarchy, macro region, clock domain, or net class
2. Root-cause hypothesis
- Most likely mechanism: <name physical or constraint mechanism>
- Competing hypothesis: <name the second plausible cause>
- Evidence still missing: <report/map/schematic/check>
3. Proposed action
- Minimal reversible fix: <physical, constraint, ECO, or methodology change>
- Expected improvement: <metric delta>
- Regression risk: False pass in one domain can hide latent yield failures.
4. Regression and signoff
- Re-run: Physical Verification closure dashboard
- Must not regress: timing, routing, power, PV, DFT, package, or tapeout signoff
- Decision owner: PD ownermechanism — Mechanism
inputs-outputs — Inputs & Outputs
reports — Reports & Metrics
debug-playbook — Debug Playbook
worked-example — Worked Example
pitfalls — Pitfalls & Red Flags
interview — Interview Drills
checklist — Review Checklist
Master Antenna and LVS Cross-Debug through reports, not GUI habit.
Physical verification is the manufacturing and connectivity gate.
DRC report grouped by rule and bounding-box cluster
LVS compare: opens, shorts, device mismatches, parameter mismatches
ERC checks: floating gates, power/ground, soft connects
density/fill report by layer and window
DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.
If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.
If DRC violations cluster, fix the systematic rule before editing isolated shapes.
If fill changes route capacitance, re-extract and re-run critical timing checks.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Lesson pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.