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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
    • DRC, LVS, and ERC Convergence Flow
    • Metal Density Fill Strategy
      • Metal Density Fill Strategy — Mechanism
      • Metal Density Fill Strategy — Inputs & Outputs
      • Metal Density Fill Strategy — Reports & Metrics
      • Metal Density Fill Strategy — Debug Playbook
      • Metal Density Fill Strategy — Worked Example
      • Metal Density Fill Strategy — Pitfalls & Red Flags
      • Metal Density Fill Strategy — Interview Drills
      • Metal Density Fill Strategy — Review Checklist
    • Antenna and LVS Cross-Debug
    • PV Waiver Policy and Auditability
    • Hierarchical LVS Debug Playbook
    • Fill and Timing Correlation
    • Systematic DRC Pattern Debug
    • Tapeout PV Signoff Gate
    • Physical Verification Tricky Q&A
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Physical Verification
  1. Topics
  2. Physical Design
  3. Physical Verification
  4. Metal Density Fill Strategy

Physical Design · All levels

Metal Density Fill Strategy

Metal Density Fill Strategy — physical design implementation and signoff.

  • 8topics
  • 8lessons

Topics in this section

  1. 1Metal Density Fill Strategy — Mechanism1 lesson
  2. 2Metal Density Fill Strategy — Inputs & Outputs1 lesson
  3. 3Metal Density Fill Strategy — Reports & Metrics1 lesson
  4. 4Metal Density Fill Strategy — Debug Playbook1 lesson
  5. 5Metal Density Fill Strategy — Worked Example1 lesson
  6. 6Metal Density Fill Strategy — Pitfalls & Red Flags1 lesson
  7. 7Metal Density Fill Strategy — Interview Drills1 lesson
  8. 8Metal Density Fill Strategy — Review Checklist1 lesson
On this page

    On-call / interview prompt

    Density fails appear near macro channels after signoff fill. Explain how you decide fill blockages versus routing relief.

    Diagram
    CLOSURE CHAIN
    
    1. METRIC     — name the failing report line (WNS, DRV, DRC count, IR %)
    2. HYPOTHESIS — 2–3 likely causes ordered by probability
    3. EXPERIMENT — one cheap check (corner, clock, report, map)
    4. FIX        — minimal physical or constraint change
    5. REGRESSION — what you re-run and what must not regress

    Topic overview

    Meet local/global density windows while preserving signal integrity, EM margin, and extraction consistency.

    Mechanism to narrate

    • Section: Physical Verification

    • Primary artifact: Density window report with pre/post-fill comparison

    • Downstream dependency: Timing and SI signoff integrity.

    Staff/principal ownership model

    Own Metal Density Fill Strategy as a release decision, not a page of notes. A senior PD engineer names the metric, the physical mechanism, the cross-team dependency, and the smallest evidence-producing experiment.

    Diagram
    STAFF REVIEW MEMO — Physical Verification / Metal Density Fill Strategy
    
    1. Current state
       - Failing / watched metric: Density window report with pre/post-fill comparison
       - Database tag, corner/mode, tool version: <fill before review>
       - Physical scope: block, hierarchy, macro region, clock domain, or net class
    
    2. Root-cause hypothesis
       - Most likely mechanism: <name physical or constraint mechanism>
       - Competing hypothesis: <name the second plausible cause>
       - Evidence still missing: <report/map/schematic/check>
    
    3. Proposed action
       - Minimal reversible fix: <physical, constraint, ECO, or methodology change>
       - Expected improvement: <metric delta>
       - Regression risk: late-stage schedule slip, silicon risk, or cross-stage regression
    
    4. Regression and signoff
       - Re-run: Density window report with pre/post-fill comparison
       - Must not regress: Timing and SI signoff integrity.
       - Decision owner: PD owner

    Sub-lessons in this topic

    1. mechanism — Mechanism

    2. inputs-outputs — Inputs & Outputs

    3. reports — Reports & Metrics

    4. debug-playbook — Debug Playbook

    5. worked-example — Worked Example

    6. pitfalls — Pitfalls & Red Flags

    7. interview — Interview Drills

    8. checklist — Review Checklist

    Related topics

    • Physical Verification hub

    Key takeaways

    • Master Metal Density Fill Strategy through reports, not GUI habit.

    Deep dive: how this shows up in real closure

    Physical verification is the manufacturing and connectivity gate.

    Reports and artifacts to inspect

    • DRC report grouped by rule and bounding-box cluster

    • LVS compare: opens, shorts, device mismatches, parameter mismatches

    • ERC checks: floating gates, power/ground, soft connects

    • density/fill report by layer and window

    Mini case study

    DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.

    Debug branches

    • If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.

    • If DRC violations cluster, fix the systematic rule before editing isolated shapes.

    • If fill changes route capacitance, re-extract and re-run critical timing checks.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Lesson pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    PreviousNext: Path Group Prioritization

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    Up nextPath Group Prioritization

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    See also

    • DRC, LVS, and ERC Convergence Flow
    • Antenna and LVS Cross-Debug
    • PV Waiver Policy and Auditability