Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
    • DRC, LVS, and ERC Convergence Flow
    • Metal Density Fill Strategy
      • Metal Density Fill Strategy — Mechanism
      • Metal Density Fill Strategy — Inputs & Outputs
      • Metal Density Fill Strategy — Reports & Metrics
      • Metal Density Fill Strategy — Debug Playbook
      • Metal Density Fill Strategy — Worked Example
      • Metal Density Fill Strategy — Pitfalls & Red Flags
      • Metal Density Fill Strategy — Interview Drills
      • Metal Density Fill Strategy — Review Checklist
    • Antenna and LVS Cross-Debug
    • PV Waiver Policy and Auditability
    • Hierarchical LVS Debug Playbook
    • Fill and Timing Correlation
    • Systematic DRC Pattern Debug
    • Tapeout PV Signoff Gate
    • Physical Verification Tricky Q&A
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
Loading lesson

‹Metal Density Fill Strategy
  1. Topics
  2. Physical Design
  3. Physical Verification
  4. Metal Density Fill Strategy
  5. Metal Density Fill Strategy — Review Checklist

Physical Design · All levels

Metal Density Fill Strategy — Review Checklist

Review Checklist for Metal Density Fill Strategy (Physical Verification).

On this page

    Review gate

    1. Inputs versioned and match RTL/SDC tag

    2. Primary metric meets spec or documented waiver

    3. Regression list executed on tagged database

    4. Risks logged with owner and date

    5. Handoff notes updated for next stage

    Smoke check (5 minutes)

    • Every checklist item has an owner

    • Failed items have mitigation or waiver ID

    Definition of done for a senior owner

    1. The exact database tag and analysis setup are recorded.

    2. The primary metric is clean or accepted by waiver: Density window report with pre/post-fill comparison.

    3. The fix is explained by mechanism, not by tool folklore.

    4. Regression coverage includes the obvious downstream domains: Timing and SI signoff integrity..

    5. Residual risk has an owner, approval path, and expiration date.

    6. The lesson is captured as a methodology guardrail if it can recur.

    Smoke check (5 minutes)

    • Could another engineer reproduce the conclusion from the notes alone?

    • Would you sign this off if the design came from another team?

    Deep dive: how this shows up in real closure

    Physical verification is the manufacturing and connectivity gate.

    Reports and artifacts to inspect

    • DRC report grouped by rule and bounding-box cluster

    • LVS compare: opens, shorts, device mismatches, parameter mismatches

    • ERC checks: floating gates, power/ground, soft connects

    • density/fill report by layer and window

    Mini case study

    DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.

    Debug branches

    • If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.

    • If DRC violations cluster, fix the systematic rule before editing isolated shapes.

    • If fill changes route capacitance, re-extract and re-run critical timing checks.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

    Previous

    474 / 709

    Next: Path Group Prioritization — Review Checklist

    Up next

    Up nextPath Group Prioritization — Review Checklist

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Metal Density Fill Strategy — Mechanism
    • Metal Density Fill Strategy — Inputs & Outputs
    • Metal Density Fill Strategy — Reports & Metrics