Data & Libraries — What PD Receives

On-call / interview prompt

You start on a new block — what data packages do you request from CAD and the RTL team before floorplan?

CLOSURE CHAIN

1. METRIC     — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX        — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regress

Essential data packages

• Technology: tech file (layers, rules), LEF (cell abstracts, pin geometry)

• Timing: liberty (.lib) per corner — slow/fast, temperature, voltage

• Physical: macro LEFs, bump/pin map, floorplan DEF template if hierarchical

• Logical: synthesized netlist or RTL + synthesis constraints (SDC)

• Power: UPF/CPF for low-power intent if applicable

File roles (quick reference)

LEF     — cell/macro pin locations, blockages, metal obstructions
DEF     — floorplan geometry, component placement, routing blockages
Liberty — cell timing (delay, slew, constraint arcs) per PVT corner
Tech    — layer stack, pitch, via rules, antenna/DRC rule hooks
NDM/CCI — unified database in modern flows (logical + physical views)
SDC     — clocks, I/O delay, exceptions — must match STA and implementation

Mechanism to narrate

• LEF abstract must match macro RTL pin order — LVS and timing depend on it.

• Liberty corner mismatch between synthesis and signoff invalidates closure.

• SDC must be version-controlled with RTL tag — stale generated clocks break CTS.

• DEF handoff between teams must include blockages and power stripes explicitly.

First-day checklist on a new block

1. Confirm corner list (BC/WC, temperature, voltage) with signoff owner.

2. Verify macro LEF revision matches RTL release notes.

3. Diff SDC against synthesis SDC — same clock definitions?

4. Load tech + LEF in viewer — spot unsupported cell heights or via stacks.

5. Document missing data in tracker before starting floorplan.

Related topics

• PD flow overview

• SDC / STA context

Key takeaways

• Bad handoff data causes weeks of debug — verify corners and LEF revision first.

• SDC is a contract between RTL, synthesis, and PD — treat it as source of truth.

Common pitfalls

• Using fast corner liberty for setup signoff at slow corner — optimistic WNS.

• Macro LEF from wrong metal stack — placement legalizer failures.

• Missing dont_touch on analog macros — optimizer breaks protected logic.

• Stale DEF from previous project reused — wrong die size and pin locations.

Data versioning hazards

Most early PD failures are bad handoffs: wrong macro LEF, stale liberty corner, mismatched SDC, or an abstract from a different IP revision. A senior PD engineer validates inputs before optimizing outputs.

Self-check

• Library corner names match signoff naming convention.

• Macro LEF revision matches IP release note.

• Rule deck, tech file, and metal stack are from the same PDK release.

Principal-level review bar

Lesson pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

• Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

• Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

• Chooses experiments by information gain and reversibility, not by habit.

• States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

• Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Interview performance is structured closure thinking under time pressure. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

• What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

• Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

• What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

• Always connect the concept back to a measurable signoff artifact.

• A fix is not complete until you can name the regression checks.

Common pitfalls

• Optimizing by habit instead of reading the current report.

• Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.