DenseChip

Physical Design · All levels

Clock Tree Synthesis

Expanded CTS registry spanning skew/latency goals, clock gating, multi-domain trees, NDR strategy, hold recovery, and debug reports.

Section goal

Build resilient clock distribution with controlled skew, bounded latency, and predictable post-CTS hold behavior.

Mechanism to narrate

  • CTS quality is validated by skew/latency compliance plus post-CTS timing stability.

  • Clock architecture choices must align with SI, power, and multi-mode constraints.

  • Report-driven debug is mandatory for hold and domain interaction issues.

Senior course bar for this section

  • Every topic should end with a signoff decision, not only concept recall.

  • Every fix should state expected metric movement and likely regression surface.

  • Every open assumption should have an owner, tag, and review date.

  • Every recurring issue should become a methodology guardrail or checklist item.

  1. cts-goals-skew-latency/ — CTS Goals: Skew, Latency, and Transition

  2. clock-gating-implementation/ — Clock Gating Implementation in CTS

  3. useful-skew-vs-structured/ — Useful Skew vs Structured Skew

  4. multi-clock-domain-cts/ — Multi-Clock Domain CTS Architecture

  5. clock-ndr-and-shielding/ — Clock NDR and Shielding Strategy

  6. post-cts-hold-fixing/ — Post-CTS Hold Fixing Workflow

  7. clock-tree-debug-reports/ — Clock Tree Debug and Report Forensics

Related topics

Key takeaways

  • CTS closure succeeds when skew control, routing strategy, and hold mitigation are planned as one system.

Detailed section notes

CTS changes the timing problem by making clocks real.

Reports and artifacts to inspect

  • clock tree summary: skew, latency, buffer count, sink count

  • clock transition and capacitance violations

  • post-CTS setup/hold WNS by clock domain

  • ICG enable timing and test-mode clock exceptions

Mini case study

Pre-CTS setup is green, but post-CTS hold WNS is -60 ps on short register-to-register paths. This is expected: clock arrival spread is now real. Add data delay or adjust skew carefully, then check setup regression.

Debug branches

  • If skew is high, inspect clock root, macro stops, NDR, and buffer placement channels.

  • If hold explodes, classify short paths by domain and add targeted delay, not global padding.

  • If ICG enable fails, debug enable path timing separately from clock skew.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

  • You are expected to predict what your fix can break before running it.

  • You should recognize when the issue is methodology, not one block's implementation.

  • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Hub pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

  • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

  • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

  • Chooses experiments by information gain and reversibility, not by habit.

  • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

  • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

diagram
STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

CTS changes the timing problem by making clocks real. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

  • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

  • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

  • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

diagram
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

  • Always connect the concept back to a measurable signoff artifact.

  • A fix is not complete until you can name the regression checks.

Common pitfalls

  • Optimizing by habit instead of reading the current report.

  • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

Practice this lesson