Post-route SI analysis shows jitter-sensitive clock degradation despite passing skew. Which NDR and shielding checks do you run first?
CLOSURE CHAIN
1. METRIC — name the failing report line (WNS, DRV, DRC count, IR %)
2. HYPOTHESIS — 2–3 likely causes ordered by probability
3. EXPERIMENT — one cheap check (corner, clock, report, map)
4. FIX — minimal physical or constraint change
5. REGRESSION — what you re-run and what must not regressApply non-default routing and shielding policies to protect clock quality against noise, variation, and congestion pressure.
Section: Clock Tree Synthesis
Primary artifact: see Reports subpage
Downstream dependency: Reliable post-route STA and silicon frequency yield require robust clock routing.
Own Clock NDR and Shielding Strategy as a release decision, not a page of notes. A senior PD engineer names the metric, the physical mechanism, the cross-team dependency, and the smallest evidence-producing experiment.
STAFF REVIEW MEMO — Clock Tree Synthesis / Clock NDR and Shielding Strategy
1. Current state
- Failing / watched metric: Clock Tree Synthesis closure dashboard
- Database tag, corner/mode, tool version: <fill before review>
- Physical scope: block, hierarchy, macro region, clock domain, or net class
2. Root-cause hypothesis
- Most likely mechanism: <name physical or constraint mechanism>
- Competing hypothesis: <name the second plausible cause>
- Evidence still missing: <report/map/schematic/check>
3. Proposed action
- Minimal reversible fix: <physical, constraint, ECO, or methodology change>
- Expected improvement: <metric delta>
- Regression risk: Insufficient NDR discipline increases jitter/SI risk and timing variability.
4. Regression and signoff
- Re-run: Clock Tree Synthesis closure dashboard
- Must not regress: Reliable post-route STA and silicon frequency yield require robust clock routing.
- Decision owner: PD ownermechanism — Mechanism
inputs-outputs — Inputs & Outputs
reports — Reports & Metrics
debug-playbook — Debug Playbook
worked-example — Worked Example
pitfalls — Pitfalls & Red Flags
interview — Interview Drills
checklist — Review Checklist
Master Clock NDR and Shielding Strategy through reports, not GUI habit.
CTS changes the timing problem by making clocks real.
clock tree summary: skew, latency, buffer count, sink count
clock transition and capacitance violations
post-CTS setup/hold WNS by clock domain
ICG enable timing and test-mode clock exceptions
Pre-CTS setup is green, but post-CTS hold WNS is -60 ps on short register-to-register paths. This is expected: clock arrival spread is now real. Add data delay or adjust skew carefully, then check setup regression.
If skew is high, inspect clock root, macro stops, NDR, and buffer placement channels.
If hold explodes, classify short paths by domain and add targeted delay, not global padding.
If ICG enable fails, debug enable path timing separately from clock skew.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Lesson pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>CTS changes the timing problem by making clocks real. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.