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Course contents

  • How to Use This Course
  • PD Flow Overview — RTL to GDSII
  • Data & Libraries — What PD Receives
  • Data and Libraries49
  • Floorplanning Expanded65
  • Power Planning57
  • Placement65
  • Clock Tree Synthesis57
    • CTS Goals: Skew, Latency, and Transition
    • Clock Gating Implementation in CTS
    • Useful Skew vs Structured Skew
    • Multi-Clock Domain CTS Architecture
    • Clock NDR and Shielding Strategy
    • Post-CTS Hold Fixing Workflow
    • Clock Tree Debug and Report Forensics
      • Clock Tree Debug and Report Forensics — Mechanism
      • Clock Tree Debug and Report Forensics — Inputs & Outputs
      • Clock Tree Debug and Report Forensics — Reports & Metrics
      • Clock Tree Debug and Report Forensics — Debug Playbook
      • Clock Tree Debug and Report Forensics — Worked Example
      • Clock Tree Debug and Report Forensics — Pitfalls & Red Flags
      • Clock Tree Debug and Report Forensics — Interview Drills
      • Clock Tree Debug and Report Forensics — Review Checklist
    • Clock Tree Synthesis Tricky Q&A
  • Routing65
  • Timing Closure81
  • Signal Integrity and Variation41
  • Power Signoff57
  • Physical Verification65
  • Physical Design Integration49
  • Signoff and Tapeout49
  • PD Interview Prep5
  • PD Closure Cheat Sheet
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‹Clock Tree Debug and Report Forensics
  1. Topics
  2. Physical Design
  3. Clock Tree Synthesis
  4. Clock Tree Debug and Report Forensics
  5. Clock Tree Debug and Report Forensics — Review Checklist

Physical Design · All levels

Clock Tree Debug and Report Forensics — Review Checklist

Review Checklist for Clock Tree Debug and Report Forensics (Clock Tree Synthesis).

On this page

    Review gate

    1. All failing metrics are categorized with owners.

    2. Constraint audits are completed before deep topology ECO.

    3. Top outliers have physical and logical explanations.

    4. Fix impact is validated on corresponding report families.

    5. Final closure packet includes reproducible forensic trail.

    Smoke check (5 minutes)

    • Every checklist item has an owner

    • Failed items have mitigation or waiver ID

    Definition of done for a senior owner

    1. The exact database tag and analysis setup are recorded.

    2. The primary metric is clean or accepted by waiver: Clock Tree Synthesis closure dashboard.

    3. The fix is explained by mechanism, not by tool folklore.

    4. Regression coverage includes the obvious downstream domains: Final STA signoff confidence and tapeout predictability depend on robust CTS forensics..

    5. Residual risk has an owner, approval path, and expiration date.

    6. The lesson is captured as a methodology guardrail if it can recur.

    Smoke check (5 minutes)

    • Could another engineer reproduce the conclusion from the notes alone?

    • Would you sign this off if the design came from another team?

    Deep dive: how this shows up in real closure

    CTS changes the timing problem by making clocks real.

    Reports and artifacts to inspect

    • clock tree summary: skew, latency, buffer count, sink count

    • clock transition and capacitance violations

    • post-CTS setup/hold WNS by clock domain

    • ICG enable timing and test-mode clock exceptions

    Mini case study

    Pre-CTS setup is green, but post-CTS hold WNS is -60 ps on short register-to-register paths. This is expected: clock arrival spread is now real. Add data delay or adjust skew carefully, then check setup regression.

    Debug branches

    • If skew is high, inspect clock root, macro stops, NDR, and buffer placement channels.

    • If hold explodes, classify short paths by domain and add targeted delay, not global padding.

    • If ICG enable fails, debug enable path timing separately from clock skew.

    Senior review question

    Ask yourself: what single report line would prove this page's concept is either passing or failing?

    What changes at 10+ years

    • You are expected to predict what your fix can break before running it.

    • You should recognize when the issue is methodology, not one block's implementation.

    • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

    Principal-level review bar

    Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

    What excellent looks like

    • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

    • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

    • Chooses experiments by information gain and reversibility, not by habit.

    • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

    • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

    Closure note template

    Diagram
    STAFF / PRINCIPAL CLOSURE NOTE
    
    Context:
      stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
      tag: <database / netlist / SDC / library stack>
      failing metric: <exact report line>
      affected scope: <block / hierarchy / path group / power domain / region>
    
    Hypotheses:
      H1: <most likely physical or constraint mechanism>
      H2: <competing explanation>
      H3: <methodology or input-data issue>
    
    Decision:
      next experiment: <cheap check that can falsify H1>
      fix candidate: <minimal reversible change>
      rollback trigger: <metric that says the fix is wrong>
      regression set: <timing / route / power / PV / DFT / package>
      escalation owner: <team or reviewer>

    Tradeoffs a senior engineer must discuss

    Technical tradeoff

    CTS changes the timing problem by making clocks real. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

    Cross-team tradeoff

    • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

    • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

    • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

    Leadership communication

    Diagram
    "The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

    Key takeaways

    • Always connect the concept back to a measurable signoff artifact.

    • A fix is not complete until you can name the regression checks.

    Common pitfalls

    • Optimizing by habit instead of reading the current report.

    • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.

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    Next: Derates and Margin Policy — Review Checklist

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    See also

    • Clock Tree Debug and Report Forensics — Mechanism
    • Clock Tree Debug and Report Forensics — Inputs & Outputs
    • Clock Tree Debug and Report Forensics — Reports & Metrics