Practice aloud for Clock Tree Synthesis → CTS Goals: Skew, Latency, and Transition. Use METRIC → HYPOTHESIS → FIX → REGRESSION.
[INT][PD][TOPIC]
Q: Why is low skew alone not enough for CTS signoff?
A:
Latency and transition quality can still break timing, power, and SI objectives even if skew is excellent.
FOLLOW-UP TRAP: Equating skew success with full CTS closure.[INT][PD][TOPIC]
Q: How do you justify different latency targets by domain?
A:
Interface and macro-adjacent domains often have tighter insertion-delay sensitivity than deep-core logic.
FOLLOW-UP TRAP: Applying uniform targets without path context.[INT][PD][TOPIC]
Q: What report pattern indicates trunk imbalance?
A:
Localized high latency and transition violations in one region despite acceptable global skew.
FOLLOW-UP TRAP: Relying only on top-line skew number.At senior/principal level, the interviewer is testing ownership judgment more than vocabulary. Answer CTS Goals: Skew, Latency, and Transition through failure mode, evidence, tradeoff, and release decision.
[INT][PD][STAFF]
Q: You inherit a late-stage CTS Goals: Skew, Latency, and Transition failure one week before release. What do you do in the first hour?
A:
Freeze the database tag, name the failing metric (Clock Tree Synthesis closure dashboard), confirm corner/mode/stage, cluster the issue, assign the first experiment, and publish a regression/owner plan before making broad tool changes.
FOLLOW-UP TRAP: Jumping directly to optimization knobs without preserving evidence.[INT][PD][STAFF]
Q: When would you stop trying to improve CTS Goals: Skew, Latency, and Transition and escalate?
A:
Escalate when the remaining risk crosses ownership boundaries, consumes shared margin, changes signed-off assumptions, or threatens Routing reserve strategy and hold-fixing burden depend on this objective setup.. Bring exact report lines and options, not vague concern.
FOLLOW-UP TRAP: Escalating without data or continuing alone after a cross-team decision is needed.CTS changes the timing problem by making clocks real.
clock tree summary: skew, latency, buffer count, sink count
clock transition and capacitance violations
post-CTS setup/hold WNS by clock domain
ICG enable timing and test-mode clock exceptions
Pre-CTS setup is green, but post-CTS hold WNS is -60 ps on short register-to-register paths. This is expected: clock arrival spread is now real. Add data delay or adjust skew carefully, then check setup regression.
If skew is high, inspect clock root, macro stops, NDR, and buffer placement channels.
If hold explodes, classify short paths by domain and add targeted delay, not global padding.
If ICG enable fails, debug enable path timing separately from clock skew.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>CTS changes the timing problem by making clocks real. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.