Fill and Timing Correlation — Worked Example

Scenario

A block encounters a Fill and Timing Correlation issue during late implementation.

Timeline

1. Metric fails at review meeting

2. Engineer captures report and layout snapshot

3. Root cause traced to incorrect assumption from prior stage

4. Minimal fix applied and documented

5. Signoff matrix re-run on tagged database

Outcome

Closure restored with documented risk and regression proof.

Senior debrief

After solving the example, write the debrief a lead would expect: what changed, why it worked, what could regress, and what permanent methodology update prevents recurrence.

STAFF REVIEW MEMO — Physical Verification / Fill and Timing Correlation

1. Current state
   - Failing / watched metric: Post-fill timing delta report with net-level RC attribution
   - Database tag, corner/mode, tool version: <fill before review>
   - Physical scope: block, hierarchy, macro region, clock domain, or net class

2. Root-cause hypothesis
   - Most likely mechanism: <name physical or constraint mechanism>
   - Competing hypothesis: <name the second plausible cause>
   - Evidence still missing: <report/map/schematic/check>

3. Proposed action
   - Minimal reversible fix: <physical, constraint, ECO, or methodology change>
   - Expected improvement: <metric delta>
   - Regression risk: late-stage schedule slip, silicon risk, or cross-stage regression

4. Regression and signoff
   - Re-run: Post-fill timing delta report with net-level RC attribution
   - Must not regress: Final STA signoff stability.
   - Decision owner: PD owner

Deep dive: how this shows up in real closure

Physical verification is the manufacturing and connectivity gate.

Reports and artifacts to inspect

• DRC report grouped by rule and bounding-box cluster

• LVS compare: opens, shorts, device mismatches, parameter mismatches

• ERC checks: floating gates, power/ground, soft connects

• density/fill report by layer and window

Mini case study

DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.

Debug branches

• If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.

• If DRC violations cluster, fix the systematic rule before editing isolated shapes.

• If fill changes route capacitance, re-extract and re-run critical timing checks.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

• You are expected to predict what your fix can break before running it.

• You should recognize when the issue is methodology, not one block's implementation.

• You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

• Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

• Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

• Chooses experiments by information gain and reversibility, not by habit.

• States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

• Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

• What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

• Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

• What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

• Always connect the concept back to a measurable signoff artifact.

• A fix is not complete until you can name the regression checks.

Common pitfalls

• Optimizing by habit instead of reading the current report.

• Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.