Practice aloud for Physical Verification → DRC, LVS, and ERC Convergence Flow. Use METRIC → HYPOTHESIS → FIX → REGRESSION.
[INT][PD][TOPIC]
Q: Explain DRC, LVS, and ERC Convergence Flow to a hiring manager in 60 seconds.
A:
Coordinate geometry, connectivity, and electrical rule checks so late-stage fixes do not oscillate between tools.
FOLLOW-UP TRAP: Tool list without mechanism.[INT][PD][TOPIC]
Q: What report proves DRC, LVS, and ERC Convergence Flow is done?
A:
Name PV summary dashboard with DRC/LVS/ERC deltas by revision and acceptance criteria.
FOLLOW-UP TRAP: No metric — only 'looks good'.[INT][PD][TOPIC]
Q: What breaks if DRC, LVS, and ERC Convergence Flow is done poorly?
A:
Uncoordinated fixes can clear one engine while reintroducing failures in another.
FOLLOW-UP TRAP: Only mentions runtime, not silicon risk.At senior/principal level, the interviewer is testing ownership judgment more than vocabulary. Answer DRC, LVS, and ERC Convergence Flow through failure mode, evidence, tradeoff, and release decision.
[INT][PD][STAFF]
Q: You inherit a late-stage DRC, LVS, and ERC Convergence Flow failure one week before release. What do you do in the first hour?
A:
Freeze the database tag, name the failing metric (PV summary dashboard with DRC/LVS/ERC deltas by revision), confirm corner/mode/stage, cluster the issue, assign the first experiment, and publish a regression/owner plan before making broad tool changes.
FOLLOW-UP TRAP: Jumping directly to optimization knobs without preserving evidence.[INT][PD][STAFF]
Q: When would you stop trying to improve DRC, LVS, and ERC Convergence Flow and escalate?
A:
Escalate when the remaining risk crosses ownership boundaries, consumes shared margin, changes signed-off assumptions, or threatens Tapeout readiness gate and foundry handoff confidence.. Bring exact report lines and options, not vague concern.
FOLLOW-UP TRAP: Escalating without data or continuing alone after a cross-team decision is needed.Physical verification is the manufacturing and connectivity gate.
DRC report grouped by rule and bounding-box cluster
LVS compare: opens, shorts, device mismatches, parameter mismatches
ERC checks: floating gates, power/ground, soft connects
density/fill report by layer and window
DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.
If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.
If DRC violations cluster, fix the systematic rule before editing isolated shapes.
If fill changes route capacitance, re-extract and re-run critical timing checks.
Ask yourself: what single report line would prove this page's concept is either passing or failing?
You are expected to predict what your fix can break before running it.
You should recognize when the issue is methodology, not one block's implementation.
You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.
Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.
Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.
Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.
Chooses experiments by information gain and reversibility, not by habit.
States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.
Turns recurring failures into methodology guardrails, dashboards, or checklist items.
STAFF / PRINCIPAL CLOSURE NOTE
Context:
stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
tag: <database / netlist / SDC / library stack>
failing metric: <exact report line>
affected scope: <block / hierarchy / path group / power domain / region>
Hypotheses:
H1: <most likely physical or constraint mechanism>
H2: <competing explanation>
H3: <methodology or input-data issue>
Decision:
next experiment: <cheap check that can falsify H1>
fix candidate: <minimal reversible change>
rollback trigger: <metric that says the fix is wrong>
regression set: <timing / route / power / PV / DFT / package>
escalation owner: <team or reviewer>Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.
What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?
Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?
What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."Always connect the concept back to a measurable signoff artifact.
A fix is not complete until you can name the regression checks.
Optimizing by habit instead of reading the current report.
Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.