Physical Design · All levels

DRC, LVS, and ERC Convergence Flow — Review Checklist

Review Checklist for DRC, LVS, and ERC Convergence Flow (Physical Verification).

Review gate

  1. Inputs versioned and match RTL/SDC tag

  2. Primary metric meets spec or documented waiver

  3. Regression list executed on tagged database

  4. Risks logged with owner and date

  5. Handoff notes updated for next stage

Smoke check (5 minutes)

  • Every checklist item has an owner

  • Failed items have mitigation or waiver ID

Definition of done for a senior owner

  1. The exact database tag and analysis setup are recorded.

  2. The primary metric is clean or accepted by waiver: PV summary dashboard with DRC/LVS/ERC deltas by revision.

  3. The fix is explained by mechanism, not by tool folklore.

  4. Regression coverage includes the obvious downstream domains: Tapeout readiness gate and foundry handoff confidence..

  5. Residual risk has an owner, approval path, and expiration date.

  6. The lesson is captured as a methodology guardrail if it can recur.

Smoke check (5 minutes)

  • Could another engineer reproduce the conclusion from the notes alone?

  • Would you sign this off if the design came from another team?

Deep dive: how this shows up in real closure

Physical verification is the manufacturing and connectivity gate.

Reports and artifacts to inspect

  • DRC report grouped by rule and bounding-box cluster

  • LVS compare: opens, shorts, device mismatches, parameter mismatches

  • ERC checks: floating gates, power/ground, soft connects

  • density/fill report by layer and window

Mini case study

DRC is clean, but LVS reports VDD opens on one hierarchical child. The right response is to inspect labels, abstract pins, and strap connectivity, not to waive connectivity.

Debug branches

  • If LVS reports opens, inspect missing vias, TEXT labels, hierarchy pins, and soft-connect settings.

  • If DRC violations cluster, fix the systematic rule before editing isolated shapes.

  • If fill changes route capacitance, re-extract and re-run critical timing checks.

Senior review question

Ask yourself: what single report line would prove this page's concept is either passing or failing?

What changes at 10+ years

  • You are expected to predict what your fix can break before running it.

  • You should recognize when the issue is methodology, not one block's implementation.

  • You should communicate risk in tapeout language: owner, evidence, impact, mitigation, and decision date.

Principal-level review bar

Deep subpage pages in this course should be read like real closure review material. For a 10+ year PD engineer, the bar is not remembering terminology; it is making a release-quality decision under ambiguity.

What excellent looks like

  • Names the failing metric, corner/mode, database tag, and analysis switches before proposing a fix.

  • Separates data, constraint, physical, tool, and methodology root causes instead of treating all failures as optimization problems.

  • Chooses experiments by information gain and reversibility, not by habit.

  • States regression blast radius across timing, route, power, PV, DFT, package, and tapeout manifest.

  • Turns recurring failures into methodology guardrails, dashboards, or checklist items.

Closure note template

diagram
STAFF / PRINCIPAL CLOSURE NOTE

Context:
  stage: <pre-CTS | post-CTS | post-route | post-fill | signoff>
  tag: <database / netlist / SDC / library stack>
  failing metric: <exact report line>
  affected scope: <block / hierarchy / path group / power domain / region>

Hypotheses:
  H1: <most likely physical or constraint mechanism>
  H2: <competing explanation>
  H3: <methodology or input-data issue>

Decision:
  next experiment: <cheap check that can falsify H1>
  fix candidate: <minimal reversible change>
  rollback trigger: <metric that says the fix is wrong>
  regression set: <timing / route / power / PV / DFT / package>
  escalation owner: <team or reviewer>

Tradeoffs a senior engineer must discuss

Technical tradeoff

Physical verification is the manufacturing and connectivity gate. Explain not only the preferred fix, but what margin or schedule you are spending to get it.

Cross-team tradeoff

  • What must RTL, synthesis, CAD, STA, DFT, package, IP, or foundry agree to before this decision is final?

  • Which artifact becomes the source of truth after the decision: report, waiver, manifest, ECO script, or methodology deck?

  • What is the cost of being wrong: one rerun, ECO churn, mask risk, performance loss, or silicon escape?

Leadership communication

diagram
"The current blocker is <metric> in <corner/mode/stage>. The leading cause is <mechanism>. I recommend <fix> because it is bounded and reversible. The regression surface is <domains>. If it fails, we escalate to <owner> with <evidence>."

Key takeaways

  • Always connect the concept back to a measurable signoff artifact.

  • A fix is not complete until you can name the regression checks.

Common pitfalls

  • Optimizing by habit instead of reading the current report.

  • Forgetting that a local fix can regress timing, routing, power, or PV elsewhere.