Stage 1 produces the map table and the link budget: proof that no two windows overlap, every base is aligned to its size, each hole answers with the right error code, and the link table names the bottleneck of the DMA stream and of CPU register traffic. Planted bugs 1 and 4 live here, plus the same-bank performance trap that halves the stream with no error flag.

Suggested order: top to bottom. The table first, because the checker needs it; decode second, because the response codes fall out of it; bandwidth last, because the burst arithmetic assumes the map is settled. The APB slot rule addr[15:12] from this stage is quoted by every later stage.