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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC14
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
      • Integration Test Plan Catching All Ten
      • Signoff Manifest and Waiver Ageing
      • Final Manifest Check and Readiness
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←Capstone: Integrate NanoSoC
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 4: Verification and Signoff

Part 14 of 14Part 14 of 14/Capstone: Integrate NanoSoCAll levels

Stage 4: Verification and Signoff

The integration test plan that catches all ten bugs, the signoff manifest with waiver ageing, and the final check.

  • 3topics
  • 3lessons

Stage 4 proves the lab: a test matrix where every planted bug has a test that passes on the clean design and fails on the injected bug, a signoff manifest generated from the stage artefacts and compared with the signed record, a waiver-ageing rule that fails stale forgiveness, and one final script that reruns every stage check and prints PASS only when all agree. The readiness review then says what is still open for silicon, including the known security hole.

Lesson

After it you can...

Integration Test Plan Catching All Ten

Write the bug-to-test matrix with no empty cell.

Signoff Manifest and Waiver Ageing

Assemble the manifest and age every waiver.

Final Manifest Check and Readiness

Run the one script that prints the manifest PASS.

Suggested order: top to bottom. The matrix first, because the manifest references its rows; the manifest second, because the final check consumes it; the final check last, because it reruns everything. No waiver in this stage may be older than its evidence.

Check yourself The matrix has ten rows and every test passes. Why is that still not a signoff?

Passing tests prove the design against the tests; the manifest must also prove the tests against the requirements, the waivers against their evidence, and the artefacts against each other.

Expect to defend a go or no-go with three open waivers: classify each by risk and evidence, name the silicon fix or software workaround, and state the decision rule before the verdict.

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See also

  • Capstone Brief
  • Stage 1: Memory Map and Interconnect
  • Stage 2: Clocks, Resets, Power